Low Complexity Detection for UTRA-TDD Receivers

Luca FANUCCI; Riccardo GRASSO

Low Complexity Detection for UTRA-TDD Receivers

Luca FANUCCI, Riccardo GRASSO

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In this paper we present the successful application of Prime Factor Algorithm FFT (Fast Fourier Transform) and pruning techniques to achieve low complexity UTRA-TDD detection. This approach has been applied to the Minimum Mean Square Error-Block Linear Equalizer (MMSE-BLE) receiver and to an MMSE equalizer specially designed for the downlink after their proper reformulation in the frequency domain. A complexity reduction of nearly 50% with respect to the classical 2ⁿ length FFT solutions has been demonstrated, without any performance loss. A more parallelizable VLSI architecture can be derived thanks to the modularity of the introduced FFT algorithms. Performances comparison has been carried out to confirm the validity of the proposed methods.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.3 pp.666-673

Publication Date: 2004/03/01

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Type of Manuscript: Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)

Category: Communication Theory and Systems

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Luca FANUCCI, Riccardo GRASSO, "Low Complexity Detection for UTRA-TDD Receivers" in IEICE TRANSACTIONS on Fundamentals, vol. E87-A, no. 3, pp. 666-673, March 2004, doi: .
Abstract: In this paper we present the successful application of Prime Factor Algorithm FFT (Fast Fourier Transform) and pruning techniques to achieve low complexity UTRA-TDD detection. This approach has been applied to the Minimum Mean Square Error-Block Linear Equalizer (MMSE-BLE) receiver and to an MMSE equalizer specially designed for the downlink after their proper reformulation in the frequency domain. A complexity reduction of nearly 50% with respect to the classical 2ⁿ length FFT solutions has been demonstrated, without any performance loss. A more parallelizable VLSI architecture can be derived thanks to the modularity of the introduced FFT algorithms. Performances comparison has been carried out to confirm the validity of the proposed methods.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_3_666/_p

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@ARTICLE{e87-a_3_666,
author={Luca FANUCCI, Riccardo GRASSO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low Complexity Detection for UTRA-TDD Receivers},
year={2004},
volume={E87-A},
number={3},
pages={666-673},
abstract={In this paper we present the successful application of Prime Factor Algorithm FFT (Fast Fourier Transform) and pruning techniques to achieve low complexity UTRA-TDD detection. This approach has been applied to the Minimum Mean Square Error-Block Linear Equalizer (MMSE-BLE) receiver and to an MMSE equalizer specially designed for the downlink after their proper reformulation in the frequency domain. A complexity reduction of nearly 50% with respect to the classical 2ⁿ length FFT solutions has been demonstrated, without any performance loss. A more parallelizable VLSI architecture can be derived thanks to the modularity of the introduced FFT algorithms. Performances comparison has been carried out to confirm the validity of the proposed methods.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Low Complexity Detection for UTRA-TDD Receivers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 666
EP - 673
AU - Luca FANUCCI
AU - Riccardo GRASSO
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2004
AB - In this paper we present the successful application of Prime Factor Algorithm FFT (Fast Fourier Transform) and pruning techniques to achieve low complexity UTRA-TDD detection. This approach has been applied to the Minimum Mean Square Error-Block Linear Equalizer (MMSE-BLE) receiver and to an MMSE equalizer specially designed for the downlink after their proper reformulation in the frequency domain. A complexity reduction of nearly 50% with respect to the classical 2ⁿ length FFT solutions has been demonstrated, without any performance loss. A more parallelizable VLSI architecture can be derived thanks to the modularity of the introduced FFT algorithms. Performances comparison has been carried out to confirm the validity of the proposed methods.
ER -