In this paper we present the successful application of Prime Factor Algorithm FFT (Fast Fourier Transform) and pruning techniques to achieve low complexity UTRA-TDD detection. This approach has been applied to the Minimum Mean Square Error-Block Linear Equalizer (MMSE-BLE) receiver and to an MMSE equalizer specially designed for the downlink after their proper reformulation in the frequency domain. A complexity reduction of nearly 50% with respect to the classical 2n length FFT solutions has been demonstrated, without any performance loss. A more parallelizable VLSI architecture can be derived thanks to the modularity of the introduced FFT algorithms. Performances comparison has been carried out to confirm the validity of the proposed methods.

A novel reconfigurable architecture has been proposed for a mobile terminal receiver that can drastically reduce power dissipation dependant on adjacent channel interference. The proposed design can automatically scale the number of filter coefficients and word length respectively by monitoring the in-band and out-of-band powers. The new architecture performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations. The UTRA-TDD downlink mode was examined statistically and results show that the reconfigurable architectures can save an average of up to 75% power dissipation respectively when compared to a fixed filter length of 57 and word length of 16 bits. This power saving only applies to the filter and ADC, not the whole receiver. This will prolong talk and standby time in a mobile terminal. The average number of taps and bits were calculated to be 14.98 and 10 respectively, for an outage of 97%.