We are trying to automate the optimum design and production of a set of physical masks for functional IC's. Our bit-map CAD for bottom-up IC design of mask pattern, coupled to a direct-write-on-wafer electron-beam (SEM) lithography system, has been used to design a D/A conversion circuit for an innerproduct multiplier so as to reduce the chip area drastically. We also have developed a program for automatic mask pattern generation from a schematic logic description. Even with parameter extractions from a trial-fabricated IC, we have been able to design and produce optimum IC's in a very short time.