BIT-MAP CAD and Electron-Beam Direct Lithography for Bottom-Up IC Design
Summary :
We are trying to automate the optimum design and production of a set of physical masks for functional IC's. Our bit-map CAD for bottom-up IC design of mask pattern, coupled to a direct-write-on-wafer electron-beam (SEM) lithography system, has been used to design a D/A conversion circuit for an innerproduct multiplier so as to reduce the chip area drastically. We also have developed a program for automatic mask pattern generation from a schematic logic description. Even with parameter extractions from a trial-fabricated IC, we have been able to design and produce optimum IC's in a very short time.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E70-E No.7 pp.641-645
- Publication Date
- 1987/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Integrated Circuits
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Katsufusa SHONO, Ryo-Il KANG, "BIT-MAP CAD and Electron-Beam Direct Lithography for Bottom-Up IC Design" in IEICE TRANSACTIONS on transactions,
vol. E70-E, no. 7, pp. 641-645, July 1987, doi: .
Abstract: We are trying to automate the optimum design and production of a set of physical masks for functional IC's. Our bit-map CAD for bottom-up IC design of mask pattern, coupled to a direct-write-on-wafer electron-beam (SEM) lithography system, has been used to design a D/A conversion circuit for an innerproduct multiplier so as to reduce the chip area drastically. We also have developed a program for automatic mask pattern generation from a schematic logic description. Even with parameter extractions from a trial-fabricated IC, we have been able to design and produce optimum IC's in a very short time.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e70-e_7_641/_p
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@ARTICLE{e70-e_7_641,
author={Katsufusa SHONO, Ryo-Il KANG, },
journal={IEICE TRANSACTIONS on transactions},
title={BIT-MAP CAD and Electron-Beam Direct Lithography for Bottom-Up IC Design},
year={1987},
volume={E70-E},
number={7},
pages={641-645},
abstract={We are trying to automate the optimum design and production of a set of physical masks for functional IC's. Our bit-map CAD for bottom-up IC design of mask pattern, coupled to a direct-write-on-wafer electron-beam (SEM) lithography system, has been used to design a D/A conversion circuit for an innerproduct multiplier so as to reduce the chip area drastically. We also have developed a program for automatic mask pattern generation from a schematic logic description. Even with parameter extractions from a trial-fabricated IC, we have been able to design and produce optimum IC's in a very short time.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - BIT-MAP CAD and Electron-Beam Direct Lithography for Bottom-Up IC Design
T2 - IEICE TRANSACTIONS on transactions
SP - 641
EP - 645
AU - Katsufusa SHONO
AU - Ryo-Il KANG
PY - 1987
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E70-E
IS - 7
JA - IEICE TRANSACTIONS on transactions
Y1 - July 1987
AB - We are trying to automate the optimum design and production of a set of physical masks for functional IC's. Our bit-map CAD for bottom-up IC design of mask pattern, coupled to a direct-write-on-wafer electron-beam (SEM) lithography system, has been used to design a D/A conversion circuit for an innerproduct multiplier so as to reduce the chip area drastically. We also have developed a program for automatic mask pattern generation from a schematic logic description. Even with parameter extractions from a trial-fabricated IC, we have been able to design and produce optimum IC's in a very short time.
ER -
English
