In the most recent processor designs, memory access latency is shortened by adopting a memory hierarchy. In this configuration, the memory consists of a main memory, which comprises dynamic random-access memory (DRAM), and a cache memory, which consists of static random-access memory (SRAM). A cache memory, which is now used in increasingly large volumes, accounts for a vast proportion of the energy consumption of the overall processor. There are two ways to reduce the energy consumption of the cache memory: by decreasing the number of accesses, and by minimizing the energy consumed per access. In this study, we reduce the size of the L1 cache by compressing frequent bit sequences, thus cutting the energy consumed per access. A “frequent bit sequence” is a specific bit pattern that often appears in high-order bits of data retained in the cache memory. Our proposed mechanism, which is based on measurements using a software simulator, cuts energy consumption by 41.0% on average as compared with conventional mechanisms.

Modern processors use Branch Target Buffer (BTB)[1] to relax control dependence. Unfortunately, the energy consumption of the BTB is high. In order to effectively fetch instructions, it is necessary to perform a branch prediction at the fetch stage, regardless of whether the fetched instruction is a branch or a nonbranch. Therefore, the number of accesses to the BTB is large, and the energy consumption of the BTB is high. However, accesses from nonbranches to the BTB waste energy. In this paper, we focus on accesses from nonbranches to the BTB, which we call useless accesses from a viewpoint of power. For reducing energy consumption without performance loss, we present a method that reduces useless accesses by using information that indicates whether a fetched instruction is a branch or not. To realize the above approach, we propose a branch bit called B-Bit. A B-Bit is associated with an instruction and indicates whether it is a branch or not. A B-Bit is available at the beginning of the fetch stage. If a B-Bit is “1” signifying a branch, the BTB is accessed. If a B-Bit is “0” signifying a nonbranch, the BTB is not accessed. The experimental results show that the total energy consumption can be reduced by 54.3% without performance loss.