We present a case of design and implementation of a high-speed burst QPSK (Quaternary Phase Shift Keying) receiver. Since the PSK modulation carries its information through the phase, the baseband digital receiver can recover transmitted symbol from the received phase. The implemented receiver estimates symbol time and frequency offset using sampled data over 32 symbols without transmitted symbol information, and embedded RAM is used for received phase delay over estimation time. The receiver is implemented using about 92,000 gates of Samsung KG75 SOG library which uses 0.65 µm CMOS technology. The fabricated chip test result shows that the receiver operates at 40 MHz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.

In modems for burst transmission of digital data, rapid carrier and clock synchronization are essential. Typically, frequency correction occurs prior to phase recovery since estimators are sensitive to frequency offsets. In this paper, we derive the bit error rate (BER) performance of a M-ary phase shift keying (MPSK) receiver in a closed form when there is no frequency offset estimator. Then we derive a relationship of the required burst length for certain BER with frequency offset estimator. To obtain the BER=10-4, approximately we need the burst length of 101 at Eb/N0=10 dB and 69 at Eb/N0=15 dB.