To design a high-speed m-bit parallel inversion circuit over GF(2m), we study two variations for the repetition-operation of the numerical formula, AB2, in employing square-first and multiply-first type operations. From the proposed two variations, we propose four inversion architectures, adopting the multiplier and square in [10], as follows: simple duplication semi-systolic architecture for multiply-first inversion circuit (MFIC), m-bit parallel semi-systolic architecture for MFIC, simple duplication semi-systolic architecture for square-first inversion circuit (SFIC), and simplified m-bit parallel semi-systolic architecture for SFIC. Among them, performance of the simplified m-bit parallel semi-systolic architecture for SFIC is recommended for a high-speed applications to get a maximum throughput in the sense of small hardware-complexity, and low latency. When we implement the simplified 8-bit parallel semi-systolic architecture for SFIC over GF(28) by using 0.25 µm CMOS library, necessary are 2495 logic-gates and 1848 latches, and the latency is 56 and the estimated clock-rate is 580 MHz at 100% throughput.

This paper proposes a novel UWB ranging scheme employing 1-bit ADCs and analog window bank for energy collection. For an appropriate 1-bit ADC process DC offset is exploited and removed via performing analog low pass filter. To improve ranging accuracy in presence of ambiguity, dual overlapped window banks designated as primary and auxiliary windows are utilized. Corresponding to the proposed ranging scheme, its performance is verified by conducting simulations in two types of channel conditions. The simulation results show that the proposed ranging scheme performs well even in condensed multipath environment and low SNR situation.

During the execution of precise ranging in the time domain, the most important fact to consider is how to achieve an accurate estimate of the time corresponding to first arrival of the transmitter. However, it is difficult to extract an estimate of the time-of-arrival (TOA) through use of a simple correlator due to degradation on correlation, and in the case where the pulse repetition interval (PRI) is less than the maximum excess delay (MED). In order to enhance the correlation capability, this paper proposes a TOA estimation method that obeys a threshold predetermined in a non-coherent system using multiple-mask operation (MMO). The performance of the proposed scheme is verified by conducting simulations under two different types of channel situations. The simulation results show that the proposed scheme performs well even in a dense indoor multipath environment and with the existence of multiple simultaneously operating piconets (SOPs).

We present a case of design and implementation of a high-speed burst QPSK (Quaternary Phase Shift Keying) receiver. Since the PSK modulation carries its information through the phase, the baseband digital receiver can recover transmitted symbol from the received phase. The implemented receiver estimates symbol time and frequency offset using sampled data over 32 symbols without transmitted symbol information, and embedded RAM is used for received phase delay over estimation time. The receiver is implemented using about 92,000 gates of Samsung KG75 SOG library which uses 0.65 µm CMOS technology. The fabricated chip test result shows that the receiver operates at 40 MHz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.