This paper proposes a novel UWB ranging scheme employing 1-bit ADCs and analog window bank for energy collection. For an appropriate 1-bit ADC process DC offset is exploited and removed via performing analog low pass filter. To improve ranging accuracy in presence of ambiguity, dual overlapped window banks designated as primary and auxiliary windows are utilized. Corresponding to the proposed ranging scheme, its performance is verified by conducting simulations in two types of channel conditions. The simulation results show that the proposed ranging scheme performs well even in condensed multipath environment and low SNR situation.

During the execution of precise ranging in the time domain, the most important fact to consider is how to achieve an accurate estimate of the time corresponding to first arrival of the transmitter. However, it is difficult to extract an estimate of the time-of-arrival (TOA) through use of a simple correlator due to degradation on correlation, and in the case where the pulse repetition interval (PRI) is less than the maximum excess delay (MED). In order to enhance the correlation capability, this paper proposes a TOA estimation method that obeys a threshold predetermined in a non-coherent system using multiple-mask operation (MMO). The performance of the proposed scheme is verified by conducting simulations under two different types of channel situations. The simulation results show that the proposed scheme performs well even in a dense indoor multipath environment and with the existence of multiple simultaneously operating piconets (SOPs).

This paper discusses the implementation of multi-band digital intermediate frequency (IF) for wideband CDMA (W-CDMA) transceiver. The majority of the implemented module in hardware is composed of wideband analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and field programmable-gated-arrays (FPGA). And in software, it is coded by VHSIC hardware description language (VHDL) for realizing digital filters and numerically controlled oscillator, etc. To cope with the hardware limitation such as the number of gates in FPGA, the overall digital filter embedded in transceiver is constructed via a cascading a series of decimation and interpolation filters. At transmitter, in order to upconvert the multi-band baseband channels simultaneously, two-stage digital complex quadrature modulation (DCQM) is utilized. The relevant up-and-down conversion of the numerically controlled oscillator (NCO) is designed in the form of a look-up-table (LUT), having samples associated with a sampled sinusoidal with period of 1/4. At receiver, to avoid the usage of surface acoustic wave (SAW) filter, the high-performance digital filter is implemented subject to satisfying band rejection ratio prescribed in blocker and adjacent channel specification. This paper provides the performance of the implemented digital IF module by revealing the results taken from the measurement instruments. Moreover, to confirm its validity computer simulations are simultaneously conducted.