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To design a high-speed *m*-bit parallel inversion circuit over GF(2^{m}), we study two variations for the repetition-operation of the numerical formula, *AB*^{2}, in employing *square-first* and *multiply-first* type operations. From the proposed two variations, we propose four inversion architectures, adopting the multiplier and square in [10], as follows: *simple duplication semi-systolic architecture for multiply-first inversion circuit (MFIC)*, *m-bit parallel semi-systolic architecture for MFIC*, *simple duplication semi-systolic architecture for square-first inversion circuit (SFIC)*, and *simplified m-bit parallel semi-systolic architecture for SFIC*. Among them, performance of the simplified *m*-bit parallel semi-systolic architecture for SFIC is recommended for a high-speed applications to get a maximum throughput in the sense of small hardware-complexity, and low latency. When we implement the *simplified 8-bit parallel semi-systolic architecture for SFIC* over GF(2^{8}) by using 0.25 µm CMOS library, necessary are 2495 logic-gates and 1848 latches, and the latency is 56 and the estimated clock-rate is 580 MHz at 100% throughput.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.11 pp.2468-2478

- Publication Date
- 2002/11/01

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- PAPER

- Category
- VLSI Design Technology and CAD

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Sungsoo CHOI, Kiseon KIM, "VLSI Architectures for High-Speed m-Bit Parallel Inversion in GF(2m) over Standard Basis" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 11, pp. 2468-2478, November 2002, doi: .

Abstract: To design a high-speed *m*-bit parallel inversion circuit over GF(2^{m}), we study two variations for the repetition-operation of the numerical formula, *AB*^{2}, in employing *square-first* and *multiply-first* type operations. From the proposed two variations, we propose four inversion architectures, adopting the multiplier and square in [10], as follows: *simple duplication semi-systolic architecture for multiply-first inversion circuit (MFIC)*, *m-bit parallel semi-systolic architecture for MFIC*, *simple duplication semi-systolic architecture for square-first inversion circuit (SFIC)*, and *simplified m-bit parallel semi-systolic architecture for SFIC*. Among them, performance of the simplified *m*-bit parallel semi-systolic architecture for SFIC is recommended for a high-speed applications to get a maximum throughput in the sense of small hardware-complexity, and low latency. When we implement the *simplified 8-bit parallel semi-systolic architecture for SFIC* over GF(2^{8}) by using 0.25 µm CMOS library, necessary are 2495 logic-gates and 1848 latches, and the latency is 56 and the estimated clock-rate is 580 MHz at 100% throughput.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_11_2468/_p

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@ARTICLE{e85-a_11_2468,

author={Sungsoo CHOI, Kiseon KIM, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={VLSI Architectures for High-Speed m-Bit Parallel Inversion in GF(2m) over Standard Basis},

year={2002},

volume={E85-A},

number={11},

pages={2468-2478},

abstract={To design a high-speed *m*-bit parallel inversion circuit over GF(2^{m}), we study two variations for the repetition-operation of the numerical formula, *AB*^{2}, in employing *square-first* and *multiply-first* type operations. From the proposed two variations, we propose four inversion architectures, adopting the multiplier and square in [10], as follows: *simple duplication semi-systolic architecture for multiply-first inversion circuit (MFIC)*, *m-bit parallel semi-systolic architecture for MFIC*, *simple duplication semi-systolic architecture for square-first inversion circuit (SFIC)*, and *simplified m-bit parallel semi-systolic architecture for SFIC*. Among them, performance of the simplified *m*-bit parallel semi-systolic architecture for SFIC is recommended for a high-speed applications to get a maximum throughput in the sense of small hardware-complexity, and low latency. When we implement the *simplified 8-bit parallel semi-systolic architecture for SFIC* over GF(2^{8}) by using 0.25 µm CMOS library, necessary are 2495 logic-gates and 1848 latches, and the latency is 56 and the estimated clock-rate is 580 MHz at 100% throughput.},

keywords={},

doi={},

ISSN={},

month={November},}

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TY - JOUR

TI - VLSI Architectures for High-Speed m-Bit Parallel Inversion in GF(2m) over Standard Basis

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2468

EP - 2478

AU - Sungsoo CHOI

AU - Kiseon KIM

PY - 2002

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E85-A

IS - 11

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - November 2002

AB - To design a high-speed *m*-bit parallel inversion circuit over GF(2^{m}), we study two variations for the repetition-operation of the numerical formula, *AB*^{2}, in employing *square-first* and *multiply-first* type operations. From the proposed two variations, we propose four inversion architectures, adopting the multiplier and square in [10], as follows: *simple duplication semi-systolic architecture for multiply-first inversion circuit (MFIC)*, *m-bit parallel semi-systolic architecture for MFIC*, *simple duplication semi-systolic architecture for square-first inversion circuit (SFIC)*, and *simplified m-bit parallel semi-systolic architecture for SFIC*. Among them, performance of the simplified *m*-bit parallel semi-systolic architecture for SFIC is recommended for a high-speed applications to get a maximum throughput in the sense of small hardware-complexity, and low latency. When we implement the *simplified 8-bit parallel semi-systolic architecture for SFIC* over GF(2^{8}) by using 0.25 µm CMOS library, necessary are 2495 logic-gates and 1848 latches, and the latency is 56 and the estimated clock-rate is 580 MHz at 100% throughput.

ER -