Six chips of the GaAs standard cell LSIs have been developed for a synchronous digital hierarchy (SDH) interface unit in 10 Gbit/s optical communication systems. Two of them are the frame termination LSIs for SDH, and four are the byte multiplexing and demultiplexing LSIs. The LSI configuration with a careful thermal design were needed to realize a natural air-cooling operation. As a result, the unit was composed of eight chips with six kind of LSIs and these LSIs consist of 1 K to 3 K gates. The LSIs were designed with the standard cell libraries based on 0.5µm gate DCFL (Direct Coupled FET Logic) operating at a low power supply voltage of 1.5V. The propagation delay time of standard DCFL inverter was 25 ps with a power consumption of 0.45mW in the experimental results. The LSI design methodology using these libraries were discussed to achieve the data processing of 1.25 Gbit/s signals under a natural air-cooling condition. The maximum operating speeds of them were at least 1.4 GHz and the power consumptions were as low as under 1.8 W, which resulted in fully high speed operations under a natural air-cooling condition at an ambient temperature of 100.

This paper describes the architecture and the performances of a GaAs 88 self-routing switch LSI for ATM switching system. The communication system such as broadband integrated sevices digital network (B-ISDN) requires the hardware switch LSI which exchanges packet cells at a date rate up to several Gb/s. GaAs LSIs are suitable for such application because of its high speed operation and low power dissipation. To clarify the feasibility of GaAs LSI, an 88 self-routing switch LSI is fabricated using 0.5 µm gate GaAs MESFETs and its oerformances are examined. This LSI consists of a switching network for exchanging the packet cells and the "NEMAWASHI" network which detects the cell destined to the same output port. The basic network architecture is a self-routing switch using Batcher-Banyan network. This network consists of basic 22 switch element. Since each element switches the route accorging to the destination of the input cells, self-routing operation is performed without the external circuit for routing control. The LSI is fabricated using 0.5 µm gate GaAs MESFETs. 7003 logic gate are integrated on the chip of 8.2 mm7.4 mm. To reduce the impedance of ground line on the chip and to obtain the enough noise margin, the third level interconnection with low sheet resistance is implemented. As the results of functional evalution, the full function of switching network and "NEMAWASHI" network are verified. Maximum operation speed of 1 GHz is obtained.

In AlGaN/GaN high electron mobility transistors (HEMTs), Si3N4 passivation film brings effective improvements in the current collapse phenomenon, however, the suppression of this phenomenon in a high voltage operation can not be achieved in only the Si3N4 deposition process. In order to solve this problem, we have demonstrated an NH3-plasma surface pretreatment in the chamber of plasma enhanced chemical vapor deposition (PE-CVD) just before Si3N4 deposition process. We found that the optimized NH3-plasma pretreatment could improve the current collapse as compared with only the Si3N4 deposition and an excessive pretreatment made it worse adversely in AlGaN/GaN-HEMTs. It was confirmed by Auger electron spectroscopy (AES) analysis that the optimized NH3-plasma pretreatment decreased the carbon contamination such as hydrocarbon on the AlGaN surface and the excessive pretreatment degraded the stoicheiometric composition of AlGaN surface.