Low pin-count testing is an effective method to reduce test cost. Based on this method multi-site testing, i.e., where multiple devices are tested concurrently, can be supported under the limitation on the number of channels provided by ATE. In this work we propose a scalable test module (called STM) design that can support multi-site testing more efficiently when compared with previous work. In the previous work, the total number of devices that can be tested concurrently is usually fixed when the design for testability hardware is designed. For our STM, each STM can deal with a number of circuits to be tested at the same time. Moreover, STM is scalable, i.e., multiple STMs can work collaboratively while the ATE bandwidth still remains the same to further increase the degree of test parallelism. Our STM will be integrated with ATE and serve as an interface between ATE and circuits under test (CUT). Only four pins are required by STM to communicate with ATE, and IEEE 1149.1 Std. ports are employed to transfer test data to/from CUTs. STM has been verified via silicon proof, which contains only about 2,768 logic gates. Experiments results for a number of ISCAS and IWLS'05 benchmark circuits also demonstrate that by making good use of the scalable feature of STM, test efficiency can be enhanced significantly.

We present a systematic and efficient way of managing the path metric memory and simplifying its connection network to the add_compare_select unit (ACSU) for Viterbi decoder (VD) design. Using the derived equations for memory partition and add-compare-select (ACS) arrangement together with the extended in-place scheduling scheme proposed in this work, we can increase the memory bandwidth for conflict-free path metric accesses with hardwired interconnection between the path metric memory and ACSU. Compared with the existing work, the developed architecture possesses the following advantages: (1) Each partitioned memory bank can be treated as a local memory of a specific processing element, inside the ACSU, with hardwired interconnection, so that the interconnect complexity is reduced significantly. (2) The partitioned memory banks can be merged into only two pseudo-banks regardless of the number of adopted ACS processing elements. This not only greatly simplifies the design of address generation unit, but also makes smaller the physical size of required memory. (3) The implementation can be accomplished in a systematic way with regular and simple controlling circuitry. Experimental results demonstrate the effectiveness of the developed architecture and the benefit will be more apparent for convolutional codes with large memory order.