An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing

Tong-Yu HSIEH; Tai-Ping WANG; Shuo YANG; Chin-An HSU; Yi-Lung LIN

doi:10.1587/transele.E99.C.404

An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing

Tong-Yu HSIEH, Tai-Ping WANG, Shuo YANG, Chin-An HSU, Yi-Lung LIN

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Low pin-count testing is an effective method to reduce test cost. Based on this method multi-site testing, i.e., where multiple devices are tested concurrently, can be supported under the limitation on the number of channels provided by ATE. In this work we propose a scalable test module (called STM) design that can support multi-site testing more efficiently when compared with previous work. In the previous work, the total number of devices that can be tested concurrently is usually fixed when the design for testability hardware is designed. For our STM, each STM can deal with a number of circuits to be tested at the same time. Moreover, STM is scalable, i.e., multiple STMs can work collaboratively while the ATE bandwidth still remains the same to further increase the degree of test parallelism. Our STM will be integrated with ATE and serve as an interface between ATE and circuits under test (CUT). Only four pins are required by STM to communicate with ATE, and IEEE 1149.1 Std. ports are employed to transfer test data to/from CUTs. STM has been verified via silicon proof, which contains only about 2,768 logic gates. Experiments results for a number of ISCAS and IWLS'05 benchmark circuits also demonstrate that by making good use of the scalable feature of STM, test efficiency can be enhanced significantly.

Publication: IEICE TRANSACTIONS on Electronics Vol.E99-C No.3 pp.404-414

Publication Date: 2016/03/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E99.C.404

Type of Manuscript: PAPER

Category: Electronic Circuits

Authors

Tong-Yu HSIEH
  National Sun Yat-sen University
Tai-Ping WANG
  ASE group
Shuo YANG
  National Sun Yat-sen University
Chin-An HSU
  National Sun Yat-sen University
Yi-Lung LIN
  ASE group

Keyword

low-pin count testing, multi-site testing, test cost, scalability, ATE utilization

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Tong-Yu HSIEH, Tai-Ping WANG, Shuo YANG, Chin-An HSU, Yi-Lung LIN, "An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing" in IEICE TRANSACTIONS on Electronics, vol. E99-C, no. 3, pp. 404-414, March 2016, doi: 10.1587/transele.E99.C.404.
Abstract: Low pin-count testing is an effective method to reduce test cost. Based on this method multi-site testing, i.e., where multiple devices are tested concurrently, can be supported under the limitation on the number of channels provided by ATE. In this work we propose a scalable test module (called STM) design that can support multi-site testing more efficiently when compared with previous work. In the previous work, the total number of devices that can be tested concurrently is usually fixed when the design for testability hardware is designed. For our STM, each STM can deal with a number of circuits to be tested at the same time. Moreover, STM is scalable, i.e., multiple STMs can work collaboratively while the ATE bandwidth still remains the same to further increase the degree of test parallelism. Our STM will be integrated with ATE and serve as an interface between ATE and circuits under test (CUT). Only four pins are required by STM to communicate with ATE, and IEEE 1149.1 Std. ports are employed to transfer test data to/from CUTs. STM has been verified via silicon proof, which contains only about 2,768 logic gates. Experiments results for a number of ISCAS and IWLS'05 benchmark circuits also demonstrate that by making good use of the scalable feature of STM, test efficiency can be enhanced significantly.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.404/_p

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@ARTICLE{e99-c_3_404,
author={Tong-Yu HSIEH, Tai-Ping WANG, Shuo YANG, Chin-An HSU, Yi-Lung LIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing},
year={2016},
volume={E99-C},
number={3},
pages={404-414},
abstract={Low pin-count testing is an effective method to reduce test cost. Based on this method multi-site testing, i.e., where multiple devices are tested concurrently, can be supported under the limitation on the number of channels provided by ATE. In this work we propose a scalable test module (called STM) design that can support multi-site testing more efficiently when compared with previous work. In the previous work, the total number of devices that can be tested concurrently is usually fixed when the design for testability hardware is designed. For our STM, each STM can deal with a number of circuits to be tested at the same time. Moreover, STM is scalable, i.e., multiple STMs can work collaboratively while the ATE bandwidth still remains the same to further increase the degree of test parallelism. Our STM will be integrated with ATE and serve as an interface between ATE and circuits under test (CUT). Only four pins are required by STM to communicate with ATE, and IEEE 1149.1 Std. ports are employed to transfer test data to/from CUTs. STM has been verified via silicon proof, which contains only about 2,768 logic gates. Experiments results for a number of ISCAS and IWLS'05 benchmark circuits also demonstrate that by making good use of the scalable feature of STM, test efficiency can be enhanced significantly.},
keywords={},
doi={10.1587/transele.E99.C.404},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing
T2 - IEICE TRANSACTIONS on Electronics
SP - 404
EP - 414
AU - Tong-Yu HSIEH
AU - Tai-Ping WANG
AU - Shuo YANG
AU - Chin-An HSU
AU - Yi-Lung LIN
PY - 2016
DO - 10.1587/transele.E99.C.404
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2016
AB - Low pin-count testing is an effective method to reduce test cost. Based on this method multi-site testing, i.e., where multiple devices are tested concurrently, can be supported under the limitation on the number of channels provided by ATE. In this work we propose a scalable test module (called STM) design that can support multi-site testing more efficiently when compared with previous work. In the previous work, the total number of devices that can be tested concurrently is usually fixed when the design for testability hardware is designed. For our STM, each STM can deal with a number of circuits to be tested at the same time. Moreover, STM is scalable, i.e., multiple STMs can work collaboratively while the ATE bandwidth still remains the same to further increase the degree of test parallelism. Our STM will be integrated with ATE and serve as an interface between ATE and circuits under test (CUT). Only four pins are required by STM to communicate with ATE, and IEEE 1149.1 Std. ports are employed to transfer test data to/from CUTs. STM has been verified via silicon proof, which contains only about 2,768 logic gates. Experiments results for a number of ISCAS and IWLS'05 benchmark circuits also demonstrate that by making good use of the scalable feature of STM, test efficiency can be enhanced significantly.
ER -