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Takashi MATSUDA Masumi ICHIEN Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO
One challenging issue of sensor networks is extension of overall network system lifetimes. In periodic data gathering applications, the typical sensor node spends more time in the idle state than active state. Consequently, it is important to decrease power consumption during idle time. In this study, we propose a scheduling scheme based on the history of RTS/CTS exchange during the setup phase. Scheduling the transmission during transfer phase enables each node to turn off its RF circuit during idle time. By tracing ongoing RTS/CTS exchange during the steady phase, each node knows the progress of the data transfer process. Thereby, it can wait to receive packets for data aggregation. Simulation results show a 160-260% longer system lifetime with the proposed scheduling scheme compared to the existing approaches.
Takashi MATSUDA Shintaro IZUMI Yasuharu SAKAI Takashi TAKEUCHI Hidehiro FUJIWARA Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO
One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. Data aggregation is one promising solution because it reduces the amount of network traffic by eliminating redundant data. In order to aggregate data, each sensor node must temporarily store received data, which requires a specific amount of memory. Most sensor nodes use static random access memory (SRAM) or flash memory for storage. SRAM can be implemented in a one-chip sensor node at low cost; however, SRAM requires standby energy, which consumes a lot of power, especially because the sensor node spends most of its time sleeping, i.e. its radio circuits are quiescent. This study proposes two types of divided SRAM: equal-size divided SRAM and equal-ratio divided SRAM. Simulations show that both proposed SRAM types offer reduced power consumption in various situations.
Shintaro IZUMI Takashi TAKEUCHI Takashi MATSUDA Hyeokjong LEE Toshihiro KONISHI Koh TSURUDA Yasuharu SAKAI Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO
This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 33 mm2 in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0 µW under a network environment.
Shintaro IZUMI Takashi TAKEUCHI Takashi MATSUDA Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO
Broadcasting is an elementary operation in wireless multi-hop networks. Flooding is a simple broadcast protocol but it frequently causes serious redundancy, contention and collisions. Probability based methods are promising because they can reduce broadcast messages without additional hardware and control packets. In this paper, the counter-based scheme which is one of the probability based methods is focused on as a broadcast protocol, and the RAD (Random Assessment Delay) Extension is proposed to improve the original counter-based scheme. The RAD Extension can be implemented without additional hardware, so that the strength of the counter-based scheme can be preserved. In addition, we propose the additional algorithm called Hop Count Aware RAD Extension to establish shorter path from the source node. Simulation results show that both of the RAD Extension and the Hop Count Aware RAD Extension reduce the number of retransmitting nodes by about 10% compared with the original scheme. Furthermore, the Hop Count Aware RAD Extension can establish almost the same path length as the counter-based scheme.