A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design

Shintaro IZUMI; Takashi TAKEUCHI; Takashi MATSUDA; Hyeokjong LEE; Toshihiro KONISHI; Koh TSURUDA; Yasuharu SAKAI; Hiroshi KAWAGUCHI; Chikara OHTA; Masahiko YOSHIMOTO

doi:10.1587/transele.E93.C.261

A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design

Shintaro IZUMI, Takashi TAKEUCHI, Takashi MATSUDA, Hyeokjong LEE, Toshihiro KONISHI, Koh TSURUDA, Yasuharu SAKAI, Hiroshi KAWAGUCHI, Chikara OHTA, Masahiko YOSHIMOTO

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This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 33 mm² in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0 µW under a network environment.

Publication: IEICE TRANSACTIONS on Electronics Vol.E93-C No.3 pp.261-269

Publication Date: 2010/03/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E93.C.261

Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)

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Shintaro IZUMI, Takashi TAKEUCHI, Takashi MATSUDA, Hyeokjong LEE, Toshihiro KONISHI, Koh TSURUDA, Yasuharu SAKAI, Hiroshi KAWAGUCHI, Chikara OHTA, Masahiko YOSHIMOTO, "A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design" in IEICE TRANSACTIONS on Electronics, vol. E93-C, no. 3, pp. 261-269, March 2010, doi: 10.1587/transele.E93.C.261.
Abstract: This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 33 mm² in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0 µW under a network environment.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.261/_p

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@ARTICLE{e93-c_3_261,
author={Shintaro IZUMI, Takashi TAKEUCHI, Takashi MATSUDA, Hyeokjong LEE, Toshihiro KONISHI, Koh TSURUDA, Yasuharu SAKAI, Hiroshi KAWAGUCHI, Chikara OHTA, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design},
year={2010},
volume={E93-C},
number={3},
pages={261-269},
abstract={This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 33 mm² in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0 µW under a network environment.},
keywords={},
doi={10.1587/transele.E93.C.261},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 261
EP - 269
AU - Shintaro IZUMI
AU - Takashi TAKEUCHI
AU - Takashi MATSUDA
AU - Hyeokjong LEE
AU - Toshihiro KONISHI
AU - Koh TSURUDA
AU - Yasuharu SAKAI
AU - Hiroshi KAWAGUCHI
AU - Chikara OHTA
AU - Masahiko YOSHIMOTO
PY - 2010
DO - 10.1587/transele.E93.C.261
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 33 mm² in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0 µW under a network environment.
ER -