We describe the design of ECL write circuits and a CMOS memory cell in an ECL-CMOS SRAM to achieve ultra-fast cycle time. Factors determining the write cycle are reduced by several novel circuit techniques and by optimizing the design of the write circuits and CMOS memory cell, thereby, enabling ultra-fast cycle time. Key techniques are a bit line overdriving, the use of an overshoot suppressing emitter follower and a WPG with a replica memory cell delayer. The 72-kb ECL-CMOS SRAM macro through which these techniques were implemented was fabricated using 0. 3-µm BiCMOS technology. The RAM macro achieves a short cycle time of 2 ns without sacrificing stable memory cell operation. These techniques thus provide SRAMs with a shorter cycle time in the cache memories of high performance computer systems.

A novel redundancy method suitable for an ultra-high-speed SRAM with logic gates is proposed. Fuse decoders are used to reduce the number of fuses, thus suppressing the access time degradation. This makes it possible to flip chip bond an SRAM with logic gates, which has a high pin count and operates at a very high frequency. To combine the new redundancy method and an ECL decoder circuit with a BiCMOS inverter, several schemes for disabling a defective cell and enabling a spare one are discussed. A 1-Mb ECL-CMOS SRAM with 120-k logic gates was fabricated using 0.3-µm BiCMOS technology. This SRAM consists of 16 RAM macros, and the RAM macro had an access time of only 0.65 ns. The access time degradation after repair was less than 50 ps.

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-µm2 memory cells has been developed using 0.3-µm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, which have been used as cache and control storages in mainframe computers.

BiCMOS circuits using a base-boost technique for low-voltage application have been proposed. These circuits can operate at supply voltages down to 1.5 V. Their power dissipation, however, is 1.5-2 times of that of the CMOS circuit. We propose a novel BiCMOS circuit dissipating less power than that of conventional circuits. A base-boost technique is a key to low-voltage operation, and a gate holding the output voltage and a depletion nMOS pre-charge transistor are also introduced to reduce the power dissipation. Results of simulations using 0.3µm BiCMOS device parameters show that base-boosted BiNMOS (BB-BiNMOS) circuit is 1.5 times faster than CMOS circuit even at 1 V and that its power dissipation is almost the same power as that of a CMOS circuit, the base-boosted BiCMOS (BB-BiCMOS) circuit is twice as fast and dissipates only 1.2 times as much power. The energy-delay product of the BB-BiCMOS circuit is smaller than that of conventional BiCMOS circuits and is about half of that of a CMOS circuit, the BB-BiCMOS circuit is thus the most promising high-speed circuits for low-voltage and low-power applications.