This paper describes a super high definition (SHD) image processing system we have developed. The computing engine of this system is a parallel processing system with 128 processing elements called NOVI- HiPIPE. A new pipelined vector processor is introduced as a backend processor of each processing element in order to meet the great computing power required by SHD image processing. This pipelined vector processor can achieve 120 MFLOPS. The 128 pipelined vector processors installed in NOVI- HiPIPE yield a total system peak performance of 15 GFLOPS. The SHD image processing system consists of an SHD image scanner, and SHD image storage node, a full color printer, a film recorder, NOVI- HiPIPE, and a Super Frame Memory. The Super Frame Memory can display a ful color moving image sequence at a rate of 60 fps on a CRT monitor at a resolution of 2048 by 2048 pixels. Workstations, interconnected through an Ethernet, are used to control these units, and SHD image data can be easily transfered among the units. NOVI- HiPIPE has a frame memory which can display SHD still images on a color monitor, therefore, one processed frame can be directly displayed. We are developing SHD image processing algorithms and parallel processing methodologies using this system.

This paper discusses the architecture and performance of parallel digital signal processing with a multicomputer system. A digital signal processor (DSP) system, called NOVI, has been developed to examine various methods for organizing parallel DSP systems, and for developing parallel programs for a wide range of digital signal processing applications. NOVI adopts multicomputer architecture and presently consists of 36 processing elements (PEs). Its parallel program development assistant (PDA) system facilitates powerful debugging functions to monitor all PEs without any interference in the parallel program execution. A load balancing technique for a multicomputer type DSP is also discussed, focusing on low bit rate motion picture coding. Finally, an example of the measured performance of the NOVI system is presented.

In this paper, we evaluate the sustained performance of the prototype SHD (Super High Definition) image processing system NOVI- HiPIPE, and discuss the requirements of a real-time SHD image processing system. NOVI- HiPIPE is a parallel DSP system with 128 PEs (Processing Elements), each containing one vector processor, and its peak performance is 15 GFLOPS. The measured performance of this system is at least 100 times higher than that of the Cray-2 (single CPU), but is still insufficient for real-time SHD image coding. When coding SHD moving images at 60 frames per second with the JPEG algorithm, the performance must be at least ten times faster than is now possible with NOVI- HiPIPE. To extract higher performance from a parallel processing system, the system architecture must be suitable for the implemented process. The advantages of NOVI- HiPIPE are its mesh network and high performance pipelined vector processor (VP), one of which is installed on each PE. When most basic SHD image coding techniques are implemented on NOVI- HiPIPE, intercommunication occurs only between directly connected PEs, and its cost is very low. Each VP can efficiently execute vector calculations. which occur frequently in image processing, and they increase the performance of NOVI- HiPIPE by a factor of from 20 to 100. In order to further improve the performance, the speed of memory access and bit operation must be increased. The next generation SHD image processing system must be built around the VP, an independent function block which controls memory access, and another block which executes bit operations. To support the input and output of SHD moving images and the inter-frame coding algorithms, the mesh network should be expanded into a 3D-cube.

Lossless video coding is required in the fields of archiving and editing digital cinema or digital broadcasting contents. This paper proposes multiresolution lossless video coding using a discrete wavelet transform and adaptive inter/intra-frame prediction in the wavelet domain. The multiresolution structure based on the wavelet transform facilitates interchange among several video source formats such as Super High Definition (SHD) images, HDTV, SDTV, and mobile applications. In order to increase the compression ratio, and to keep the computational cost low, the adaptive inter/intra-frame prediction is performed in the lowest wavelet transform domain. The adaptive inter/intra-frame prediction can adapt to changes in the local inter/intra-frame statistics. Experiments on digital cinema test sequences confirm effectiveness of the proposed algorithm.

This paper discusses the bit-rate compression of super high definition still images with subband coding. Super high definition (SHD) images with more than 20482048 pixels or resolution are introduced as the next generation imaging system beyond HDTV. In order to develop bit-rate reduction algorithms, an image evaluation system for super high definition images is assembled. Signal characteristics are evaluated and the optimum subband analysis/synthesis system for the SHD images is clarified. A scalar quantization combined with run-length and Huffman coding is introduced as a conventional subband coding algorithm, and its coding performance is evaluated for SHD images. Finally, new coding algorithms based on block Huffman coding and entropy coded vector quantization are proposed. SNR improvement of 0.5 dB and 1.0 dB can be achieved with the proposed block Huffman coding and the vector quantization algorithm, respectively.