The singular points of fingerprints, viz. core and delta, are important referential points for the classification of fingerprints. Several conventional approaches such as the Poincare index method have been proposed; however, these approaches are not reliable with poor-quality fingerprints. This paper proposes a new core and delta detection employing singular candidate analysis and an extended relational graph. Singular candidate analysis allows the use both the local and global features of ridge direction patterns and realizes high tolerance to local image noise; this involves the extraction of locations where there is high probability of the existence of a singular point. Experimental results using the fingerprint image databases FVC2000 and FVC2002, which include several poor-quality images, show that the success rate of the proposed approach is 10% higher than that of the Poincare index method for singularity detection, although the average computation time is 15%-30% greater.

This paper describes a new approach to detect a fingerprint core location using the extended relational graph, which is generated by the segmentation of the ridge directional image. The extended relational graph presents the adjacency between segments of the directional image and the boundary information between segments of the directional image. The boundary curves generated by the boundary information in the extended relational graph is approximated to the straight lines. The fingerprint core location is calculated as center of the gravity in the points of intersection of these approximated lines. Experimental results show that 90.8% of the 130 fingerprint samples are succeeded to detect the core location.

The paper presents the improvement of out new approach to optimize the process parameter variation, device heat and wire parasitics for analog LSI design by explicitly incorporating various performance estimations into objective functions for placement and routing. To minimize these objective functions, the placement by the simulated annealing method, and maze routing are effectively modified with the perfomance estimation. The improvement results in the excellent performance driven layout for the large size of analog LSIs.

This paper describes a new approach towards the performance-driven layout for analog LSIs. Based on our approach, we developed an automatic performance-driven layout system LIBRA. The performance-driven layout has an advantage that numerical evaluations of performance requirements may exactly specify layout requirements so that a better layout result will be expected with regard to both the size and the performances. As the first step to the final goal, we only concern with the DC characteristics of analog circuits affected by the placement and routing. First of all, LIBRA performs the sensitivity analysis with respect to process parameters and wire parasitics, which are major causes for DC performance deviations of analog LSIs, so as to describe every perfomance deviation by its first order approximation. Based on the estimations of those performance deviations, LIBRA designs the placement of devices. The placement approach here is the simulated annealing method driven by their circuit performance specification. The routing of inter-cell wires is performed according to the priority of the larger total wire sensitivities in the net by the maze router. Then, the simple compaction eliminates the empty space as much as possible. After that, the power lines optimization is performed so as to minimize the ferformance deviations. Finally, an advantage of the performance improvement by our approach is demonstrated by showing a layout result of a practical bipolar circuit and its excellent performance evaluations.

A new detection methodology for both of the core and the delta of the fingerprint using the extended relational graph is presented. This paper shows the way to detect both of the core loop and the delta loop from the extended relational graph, which we proposed in order to summarize the global feature of the fingerprint ridge pattern distribution. The experimental results for 180 fingerprint samples show that the processing time is ranging from 0.34 [sec] to 0.44 [sec] for each fingerprint image by using Pentium 4 1.8 GHz Processor. In our experiments, the core and the delta were successfully extracted in 94.4% of the 180 samples.

In this paper, a LSI design for video encoder and decoder for H.263+ video compression is presented. LSI operates under clock frequency of 27 MHz to compress QCIF (176144 pixels) at the frame rate of 30 frame per second. The core size is 4.6 4.6 mm2 in a 0.35 µm process. The architecture is based on bus connected heterogeneous dedicated modules, named as System-MSPA architecture. It employs the fast and small-chip-area dedicated modules in lower level and controls them by employing the slow and flexible programmable device and an external DRAM. Design results in success to achieve real time encoder in quite compact size without losing flexibility and expand ability. Real time emulation and easy test capability with external PC is also implemented.