System-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications

Chawalit HONSAWEK, Kazuhito ITO, Tomohiko OHTSUKA, Trio ADIONO, Dongju LI, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA

Summary :

In this paper, a LSI design for video encoder and decoder for H.263+ video compression is presented. LSI operates under clock frequency of 27 MHz to compress QCIF (176144 pixels) at the frame rate of 30 frame per second. The core size is 4.6 4.6 mm² in a 0.35 µm process. The architecture is based on bus connected heterogeneous dedicated modules, named as System-MSPA architecture. It employs the fast and small-chip-area dedicated modules in lower level and controls them by employing the slow and flexible programmable device and an external DRAM. Design results in success to achieve real time encoder in quite compact size without losing flexibility and expand ability. Real time emulation and easy test capability with external PC is also implemented.

• Publication: IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.11 pp.2614-2622
• Publication Date: 2001/11/01
• Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
• Category: VLSI Design

Authors

Chawalit HONSAWEK
Kazuhito ITO
Tomohiko OHTSUKA
Trio ADIONO
Dongju LI
Tsuyoshi ISSHIKI
Hiroaki KUNIEDA

Keyword

system-MSPA,  LSI design,  videotelephony applications,  H.263+ ITU standard