In this paper, we propose a method for constructing quasi-cyclic low-density parity-check codes randomly using cyclic shift submatrices on the basis of the girth of the Tanner graphs of these codes. We consider (3, K)-regular codes and first derive the necessary and sufficient conditions for weight-4 and weight-6 codewords to exist. On the basis of these conditions, it is possible to estimate the probability that a random method will generate a (3, K)-regular code with a minimum distance less than or equal to 6, and the proposed method is shown to offer a lower probability than does conventional random construction. Simulation results also show that it is capable of generating good codes both regular and irregular.

Outsourcing IC design and fabrication is one of the effective solutions to reduce design cost but it may cause severe security risks. Particularly, malicious outside vendors may implement Hardware Trojans (HTs) on ICs. When we focus on IC design phase, we cannot assume an HT-free netlist or a Golden netlist and it is too difficult to identify whether a given netlist is HT-free or not. In this paper, we propose a score-based hardware-trojans identifying method at gate-level netlists without using a Golden netlist. Our proposed method does not directly detect HTs themselves in a gate-level netlist but it detects a net included in HTs, which is called Trojan net, instead. Firstly, we observe Trojan nets from several HT-inserted benchmarks and extract several their features. Secondly, we give scores to extracted Trojan net features and sum up them for each net in benchmarks. Then we can find out a score threshold to classify HT-free and HT-inserted netlists. Based on these scores, we can successfully classify HT-free and HT-inserted netlists in all the Trust-HUB gate-level benchmarks and ISCAS85 benchmarks as well as HT-free and HT-inserted AES gate-level netlists. Experimental results demonstrate that our method successfully identify all the HT-inserted gate-level benchmarks to be “HT-inserted” and all the HT-free gate-level benchmarks to be “HT-free” in approximately three hours for each benchmark.

Since digital ICs are often designed and fabricated by third parties at any phases today, we must eliminate risks that malicious attackers may implement Hardware Trojans (HTs) on them. In particular, they can easily insert HTs during design phase. This paper proposes an HT rank which is a new quantitative analysis criterion against HTs at gate-level netlists. We have carefully analyzed all the gate-level netlists in Trust-HUB benchmark suite and found out several Trojan net features in them. Then we design the three types of Trojan points: feature point, count point, and location point. By assigning these points to every net and summing up them, we have the maximum Trojan point in a gate-level netlist. This point gives our HT rank. The HT rank can be calculated just by net features and we do not perform any logic simulation nor random test. When all the gate-level netlists in Trust-HUB, ISCAS85, ISCAS89 and ITC99 benchmark suites as well as several OpenCores designs, HT-free and HT-inserted AES netlists are ranked by our HT rank, we can completely distinguish HT-inserted ones (which HT rank is ten or more) from HT-free ones (which HT rank is nine or less). The HT rank is the world-first quantitative criterion which distinguishes HT-inserted netlists from HT-free ones in all the gate-level netlists in Trust-HUB, ISCAS85, ISCAS89, and ITC99.

Incremental Redundancy Hybrid ARQ (IR-HARQ) based on rate-compatible punctured low-density parity-check (LDPC) codes can achieve high throughput over a wide range of SNRs. One drawback of such IR-HARQ schemes is high computational complexity of decoding for early transmission at high rates. In order to overcome this problem, a HARQ scheme based on rate-compatible LDPC codes by shortening and extending is presented in this paper. In the HARQ scheme, a high-rate mother code is transmitted at first, and parity-bits of a shortened code are transmitted for early retransmission requests. With a low-complexity decoder of the high-rate mother code, this shortened-code approach would result in low computational complexity of decoding, but it causes smaller length and larger number of shortened codes to be decoded as retransmission repeats. To prevent the resultant degradation of performance and complexity, extending is efficiently applied to the shortened codes after predetermined retransmission-times. A multi-edge type code-design is employed to construct irregular LDPC codes that meet the requirement of the HARQ scheme. Simulation results show that the HARQ scheme can achieve lower computational complexity of decoding than a conventional IR-HARQ scheme with good throughput over a wide range of SNRs.

This paper gives an overview of Turbo codes principles, performance, and design issues for practical application. As fundamentals of Turbo codes, encoder structure, interleaver, and iterative decoding are explained. The performance is analyzed through their weight distribution, and the analysis gives code design rules for component codes. Practical decoding algorithms are presented in addition to MAP algorithm. Design issues are discussed for mobile communications as an example of practical application. Finally, research trends are briefly mentioned.