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[Author] Tsunehiro HATO(3hit)

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  • Recent Developments of High-Tc Electronic Devices with Multilayer Structures and Ramp-Edge Josephson Junctions Open Access

    Seiji ADACHI  Akira TSUKAMOTO  Tsunehiro HATO  Joji KAWANO  Keiichi TANABE  

     
    INVITED PAPER

      Vol:
    E95-C No:3
      Page(s):
    337-346

    Recent developments of electronic devices containing Josephson junctions (JJ) with high-Tc superconductors (HTS) are reported. In particular, the fabrication process and the properties of superconducting quantum interference devices (SQUIDs) with a multilayer structure and ramp-edge-type JJs are described. The JJs were fabricated by recrystallization of an artificially deposited Cu-poor precursory layer. The formation mechanism of the junction barrier is discussed. We have fabricated various types of gradiometers and magnetometers. They have been actually utilized for several application systems, such as a non-destructive evaluation (NDE) system for deep-lying defects in a metallic plate and a reel-to-reel testing system for striated HTS-coated conductors.

  • Advances in High-Tc Single Flux Quantum Device Technologies

    Keiichi TANABE  Hironori WAKANA  Koji TSUBONE  Yoshinobu TARUTANI  Seiji ADACHI  Yoshihiro ISHIMARU  Michitaka MARUYAMA  Tsunehiro HATO  Akira YOSHIDA  Hideo SUZUKI  

     
    INVITED PAPER

      Vol:
    E91-C No:3
      Page(s):
    280-292

    We have developed the fabrication process, the circuit design technology, and the cryopackaging technology for high-Tc single flux quantum (SFQ) devices with the aim of application to an analog-to-digital (A/D) converter circuit for future wireless communication and a sampler system for high-speed measurements. Reproducibility of fabricating ramp-edge Josephson junctions with IcRn products above 1 mV at 40 K and small Ic spreads on a superconducting groundplane was much improved by employing smooth multilayer structures and optimizing the junction fabrication process. The separated base-electrode layout (SBL) method that suppresses the Jc spread for interface-modified junctions in circuits was developed. This method enabled low-frequency logic operations of various elementary SFQ circuits with relatively wide bias current margins and operation of a toggle-flip-flop (T-FF) above 200 GHz at 40 K. Operation of a 1:2 demultiplexer, one of main elements of a hybrid-type Σ-Δ A/D converter circuit, was also demonstrated. We developed a sampler system in which a sampler circuit with a potential bandwidth over 100 GHz was cooled by a compact stirling cooler, and waveform observation experiments confirmed the actual system bandwidth well over 50 GHz.

  • HTS Sampler with Improved Circuit Design and Layout

    Michitaka MARUYAMA  Hironori WAKANA  Tsunehiro HATO  Hideo SUZUKI  Keiichi TANABE  Koichiro UEKUSA  Takeshi KONNO  Nobuya SATO  Masayuki KAWABATA  

     
    INVITED PAPER

      Vol:
    E90-C No:3
      Page(s):
    579-587

    This paper reviews our progress on the high-Tc superconducting (HTS) sampler development, covering from the circuit design to the latest experimental data in the sinusoidal and pulse waveform measurements. A computer simulation has revealed that our sampler circuit with an improved design enables waveform measurement with the bandwidth over 100 GHz even with the thermal noise at around 40 K. Using the HTS sampler circuits fabricated employing an improved layout, we demonstrated waveform measurements for sinusoidal signals with frequencies of up to 50 GHz, the upper limit of the signal generator we used, both in the voltage-input-type system with a high-frequency input line and in the current-input-type one with a superconducting pickup coil. In the pulse measurement using an on-chip sampler, we succeeded in observing pico-second-order-wide single flux quantum (SFQ) current pulses, suggesting the potential bandwidth of our HTS sampler of more than 125 GHz.