The so-called numerical alphabet has been established as one of the various memorization systems. It enables numbers to be transformed into words. In that way memorizing numbers is highly alleviated, since words are to be memorized instead of numbers, which is substantially easier. In order to master the technique of transforming numbers into words (for memorizing them), as well as transforming words back to numbers, a person has to practice. Upon adopting the numerical alphabet, one then has to practice various examples and translate numbers into proper words and words into proper numbers. This paper describes the computer application we have developed that helps in this process. To our knowledge, this is the first complete application of this type ever created. We also show the results of the students' number-memorization tests, performed before and after using the application, which show significant improvements.

In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.

In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They can suppress the latencies when accessing cache or main memory. In our previous work we proposed predictors that not only close the opened DRAM row but also predict the next row to be opened, hence the name ‘Complete Predictor’. It requires less than 10kB of SRAM for a 2GB SDRAM system. In this paper we evaluate how much additional hardware is needed and whether the activations of the predictors will slow down the DRAM controller.

In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They enable hiding the latencies when accessing cache or main memory. In our previous work we proposed a DDR SDRAM controller with predictors that not only close the opened DRAM row but also predict the next row to be opened. In this paper we explore the possibilities of trying the same techniques on the latest type of DRAM memory, DDR3 SDRAM, with further improvements of the predictors.