IEICE TRANSACTIONS on Information
DRAM Controller with a Complete Predictor
Summary :
In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.
- Publication
- IEICE TRANSACTIONS on Information Vol.E92-D No.4 pp.584-593
- Publication Date
- 2009/04/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E92.D.584
- Type of Manuscript
- PAPER
- Category
- Computer Systems
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Keyword
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Vladimir V. STANKOVIC, Nebojsa Z. MILENKOVIC, "DRAM Controller with a Complete Predictor" in IEICE TRANSACTIONS on Information,
vol. E92-D, no. 4, pp. 584-593, April 2009, doi: 10.1587/transinf.E92.D.584.
Abstract: In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.584/_p
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@ARTICLE{e92-d_4_584,
author={Vladimir V. STANKOVIC, Nebojsa Z. MILENKOVIC, },
journal={IEICE TRANSACTIONS on Information},
title={DRAM Controller with a Complete Predictor},
year={2009},
volume={E92-D},
number={4},
pages={584-593},
abstract={In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.},
keywords={},
doi={10.1587/transinf.E92.D.584},
ISSN={1745-1361},
month={April},}
Copy
TY - JOUR
TI - DRAM Controller with a Complete Predictor
T2 - IEICE TRANSACTIONS on Information
SP - 584
EP - 593
AU - Vladimir V. STANKOVIC
AU - Nebojsa Z. MILENKOVIC
PY - 2009
DO - 10.1587/transinf.E92.D.584
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2009
AB - In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.
ER -
English
