In this paper, we propose a fast algorithm to realize parallel median filter for processing 1-D and 2-D signal. In the proposed pipelined architecture, m-passes are employed for filtering signal while word resolution is m bits. One pass employs one processing element (PE), and the number of PEs is independent of the number of samples. Therefore, we only need m PEs for real-time operation. With 8-bits resolution, the system gate-count is less than 5 k. Moreover, this median architecture could be easily modified to consist of the programmable feature that may choose the better sampling number to filter signal. It should be also noted that our proposed processing flow has a progressive property, which is very suitable for bandwidth-limited channel application.