A Parallel Median Filter with Pipelined Scheduling for Real-Time 1D and 2D Signal Processing
Summary :
In this paper, we propose a fast algorithm to realize parallel median filter for processing 1-D and 2-D signal. In the proposed pipelined architecture, m-passes are employed for filtering signal while word resolution is m bits. One pass employs one processing element (PE), and the number of PEs is independent of the number of samples. Therefore, we only need m PEs for real-time operation. With 8-bits resolution, the system gate-count is less than 5 k. Moreover, this median architecture could be easily modified to consist of the programmable feature that may choose the better sampling number to filter signal. It should be also noted that our proposed processing flow has a progressive property, which is very suitable for bandwidth-limited channel application.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.7 pp.1396-1404
- Publication Date
- 2000/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Shih-Chang HSIA, Wei-Chih HSU, "A Parallel Median Filter with Pipelined Scheduling for Real-Time 1D and 2D Signal Processing" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 7, pp. 1396-1404, July 2000, doi: .
Abstract: In this paper, we propose a fast algorithm to realize parallel median filter for processing 1-D and 2-D signal. In the proposed pipelined architecture, m-passes are employed for filtering signal while word resolution is m bits. One pass employs one processing element (PE), and the number of PEs is independent of the number of samples. Therefore, we only need m PEs for real-time operation. With 8-bits resolution, the system gate-count is less than 5 k. Moreover, this median architecture could be easily modified to consist of the programmable feature that may choose the better sampling number to filter signal. It should be also noted that our proposed processing flow has a progressive property, which is very suitable for bandwidth-limited channel application.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_7_1396/_p
Copy
@ARTICLE{e83-a_7_1396,
author={Shih-Chang HSIA, Wei-Chih HSU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Parallel Median Filter with Pipelined Scheduling for Real-Time 1D and 2D Signal Processing},
year={2000},
volume={E83-A},
number={7},
pages={1396-1404},
abstract={In this paper, we propose a fast algorithm to realize parallel median filter for processing 1-D and 2-D signal. In the proposed pipelined architecture, m-passes are employed for filtering signal while word resolution is m bits. One pass employs one processing element (PE), and the number of PEs is independent of the number of samples. Therefore, we only need m PEs for real-time operation. With 8-bits resolution, the system gate-count is less than 5 k. Moreover, this median architecture could be easily modified to consist of the programmable feature that may choose the better sampling number to filter signal. It should be also noted that our proposed processing flow has a progressive property, which is very suitable for bandwidth-limited channel application.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - A Parallel Median Filter with Pipelined Scheduling for Real-Time 1D and 2D Signal Processing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1396
EP - 1404
AU - Shih-Chang HSIA
AU - Wei-Chih HSU
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2000
AB - In this paper, we propose a fast algorithm to realize parallel median filter for processing 1-D and 2-D signal. In the proposed pipelined architecture, m-passes are employed for filtering signal while word resolution is m bits. One pass employs one processing element (PE), and the number of PEs is independent of the number of samples. Therefore, we only need m PEs for real-time operation. With 8-bits resolution, the system gate-count is less than 5 k. Moreover, this median architecture could be easily modified to consist of the programmable feature that may choose the better sampling number to filter signal. It should be also noted that our proposed processing flow has a progressive property, which is very suitable for bandwidth-limited channel application.
ER -
English
