Efficient extraction of interconnect parasitic parameters has become very important for present deep submicron designs. In this paper, the improved boundary element method (BEM) is presented for 3-D interconnect resistance extraction. The BEM is accelerated by the recently proposed quasi-multiple medium (QMM) technology, which quasi-cuts the calculated region to enlarge the sparsity of the overall coefficient matrix to solve. An un-average quasi-cutting scheme for QMM, advanced nonuniform element partition and technique of employing the linear element for some special surfaces are proposed. These improvements considerably condense the computational resource of the QMM-based BEM without loss of accuracy. Experiments on actual layout cases show that the presented method is several hundred to several thousand times faster than the well-known commercial software Raphael, while preserving the high accuracy.

This paper introduces a step response based method to predict the eye diagram for high-speed signaling systems. The method is able to predict accurately the worst-case eye diagram, and is orders of magnitude faster than the method using SPICE simulation with input of random bits. The proposed method is applied to search optimal equalizer parameters for lower-power transmission-line signaling schemes. Simulation results show that the scheme with driver-side series capacitor achieves much better eye area, and signaling throughput than the conventional scheme with only resistive terminations.

In this paper, an efficient method is proposed to accurately analyze large-scale power/ground (P/G) networks, where inductive parasitics are modeled with the partial reluctance. The method is based on frequency-domain circuit analysis and the technique of vector fitting, and obtains the time-domain voltage response at given P/G nodes. The frequency-domain circuit equation including partial reluctances is derived, and then solved with the GMRES algorithm with rescaling, preconditioning and recycling techniques. With the merit of sparsified reluctance matrix and iterative solving techniques for the frequency-domain circuit equations, the proposed method is able to handle large-scale P/G networks with complete inductive modeling. Numerical results show that the proposed method is orders of magnitude faster than HSPICE, several times faster than INDUCTWISE, and capable of handling the inductive P/G structures with more than 100,000 wire segments.

Inductive effect becomes important for on-chip global interconnects, like the power/ground (P/G) grid. Because of the locality property of partial reluctance, the inverse of partial inductance, the window-based partial reluctance extraction has been applied for large-scale interconnect structures. In this paper, an efficient method of partial reluctance extraction is proposed for large-scale regular P/G grid structures. With a block reuse technique, the proposed method makes full use of the structural regularity of the P/G grid. Numerical results demonstrate the proposed method is able to efficiently handle a P/G grid with up to one hundred thousands wire segments. It is several tens times faster than the window-based method, while generating accurate frequency-dependent partial reluctance and resistance.