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[Author] Xiangyu MENG(2hit)

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  • A Low Power 100-Gb/s PAM-4 Driver with Linear Distortion Compensation in 65-nm CMOS

    Xiangyu MENG  Kangfeng WEI  Zhiyi YU  Xinlun CAI  

     
    PAPER-Electronic Circuits

      Pubricized:
    2022/07/01
      Vol:
    E106-C No:1
      Page(s):
    7-13

    This paper proposes a low-power 100Gb/s four-level pulse amplitude modulation driver (PAM-4 Driver) based on linear distortion compensation structure for thin-film Lithium Niobate (LiNbO3) modulators, which manages to achieve high linearity in the output. The inductive peaking technology and open drain structure enable the overall circuit to achieve a 31-GHz bandwidth. With an area of 0.292 mm2, the proposed PAM-4 driver chip is designed in a 65-nm process to achieve power consumption of 37.7 mW. Post-layout simulation results show that the power efficiency is 0.37 mW/Gb/s, RLM is more than 96%, and the FOM value is 8.84.

  • A Low Insertion Loss Wideband Bonding-Wire Based Interconnection for 400 Gbps PAM4 Transceivers

    Xiangyu MENG  Yecong LI  Zhiyi YU  

     
    PAPER-Electronic Components

      Pubricized:
    2022/06/23
      Vol:
    E106-C No:1
      Page(s):
    14-19

    This paper proposes a design of high-speed interconnection between optical modules and electrical modules via bonding-wires and coplanar waveguide transmission lines on printed circuit boards for 400 Gbps 4-channel optical communication systems. In order to broaden the interconnection bandwidth, interdigitated capacitors were integrated with GSG pads on chip for the first time. Simulation results indicate the reflection coefficient is below -10 dB from DC to 53 GHz and the insertion loss is below 1 dB from DC to 45 GHz. Both indicators show that the proposed interconnection structure can effectively satisfy the communication bandwidth requirements of 100-Gbps or even higher data-rate PAM4 signals.