This paper proposes a novel RBF training algorithm based on immune operations for dynamic problem solving. The algorithm takes inspiration from the dynamic nature of natural immune system and locally-tuned structure of RBF neural network. Through immune operations of vaccination and immune response, the RBF network can dynamically adapt to environments according to changes in the training set. Simulation results demonstrate that RBF equalizer based on the proposed algorithm obtains good performance in nonlinear time-varying channels.

In this paper, we study simultaneous wireless information and power transfer (SWIPT) in two-way relay channels where two users exchange information with each other via a multi-antenna relay node. The signals forwarded by the relay node are also used to supply the power to two users. We formulate a max-min optimization problem aiming to maximize the minimum harvested energy between two users to achieve fairness. We jointly optimize the relay beamforming matrix and allocating powers at the two users subject to the quality of service (QoS) constraints. To be specific, we consider the amplify-and-forward (AF) relay strategy and the time splitting SWIPT strategy. To this end, we propose two different time splitting protocols to enable relay to supply power to two users. To solve the non-convex joint optimization problem, we propose to split the original optimization problem into two subproblems and solving them iteratively to obtain the final solution. It is shown that the first subproblem dealing with the beamforming matrix can be optimally solved by using the technique of relaxed semidefinite programming (SDR), and the second subproblem, which deals with the power allocation, can be solved via linear programming. The performance comparison of two schemes as well as the one-way relaying scheme are provided and the effectiveness of the proposed schemes is verified.

In this letter, an area-efficient architecture for the hardware implementation of the real-time prime factor Fourier transform (PFFT) is presented. In the proposed architecture, a prime length DFT module with the one-point-per-cycle (OPPC) property is implemented by the parallel distributed arithmetic (DA), and a cyclic convolution feature is exploited to simplify the structure of the DA cells. Based on the proposed architecture, a real-time 65-point PFFT processor is designed, and the synthesis results show that it saves over 8% gates compared to the existing real-time 64-point DFT designs.