IEICE TRANSACTIONS on Fundamentals
An Area Efficient Real-Time PFFT Architecture Using Parallel Distributed Arithmetic
Summary :
In this letter, an area-efficient architecture for the hardware implementation of the real-time prime factor Fourier transform (PFFT) is presented. In the proposed architecture, a prime length DFT module with the one-point-per-cycle (OPPC) property is implemented by the parallel distributed arithmetic (DA), and a cyclic convolution feature is exploited to simplify the structure of the DA cells. Based on the proposed architecture, a real-time 65-point PFFT processor is designed, and the synthesis results show that it saves over 8% gates compared to the existing real-time 64-point DFT designs.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.2 pp.600-603
- Publication Date
- 2012/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.600
- Type of Manuscript
- LETTER
- Category
- Digital Signal Processing
Authors
Keyword
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Xiaofeng LING, Xinbao GONG, Xiaogang ZANG, Ronghong JIN, "An Area Efficient Real-Time PFFT Architecture Using Parallel Distributed Arithmetic" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 2, pp. 600-603, February 2012, doi: 10.1587/transfun.E95.A.600.
Abstract: In this letter, an area-efficient architecture for the hardware implementation of the real-time prime factor Fourier transform (PFFT) is presented. In the proposed architecture, a prime length DFT module with the one-point-per-cycle (OPPC) property is implemented by the parallel distributed arithmetic (DA), and a cyclic convolution feature is exploited to simplify the structure of the DA cells. Based on the proposed architecture, a real-time 65-point PFFT processor is designed, and the synthesis results show that it saves over 8% gates compared to the existing real-time 64-point DFT designs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.600/_p
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@ARTICLE{e95-a_2_600,
author={Xiaofeng LING, Xinbao GONG, Xiaogang ZANG, Ronghong JIN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Area Efficient Real-Time PFFT Architecture Using Parallel Distributed Arithmetic},
year={2012},
volume={E95-A},
number={2},
pages={600-603},
abstract={In this letter, an area-efficient architecture for the hardware implementation of the real-time prime factor Fourier transform (PFFT) is presented. In the proposed architecture, a prime length DFT module with the one-point-per-cycle (OPPC) property is implemented by the parallel distributed arithmetic (DA), and a cyclic convolution feature is exploited to simplify the structure of the DA cells. Based on the proposed architecture, a real-time 65-point PFFT processor is designed, and the synthesis results show that it saves over 8% gates compared to the existing real-time 64-point DFT designs.},
keywords={},
doi={10.1587/transfun.E95.A.600},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - An Area Efficient Real-Time PFFT Architecture Using Parallel Distributed Arithmetic
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 600
EP - 603
AU - Xiaofeng LING
AU - Xinbao GONG
AU - Xiaogang ZANG
AU - Ronghong JIN
PY - 2012
DO - 10.1587/transfun.E95.A.600
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2012
AB - In this letter, an area-efficient architecture for the hardware implementation of the real-time prime factor Fourier transform (PFFT) is presented. In the proposed architecture, a prime length DFT module with the one-point-per-cycle (OPPC) property is implemented by the parallel distributed arithmetic (DA), and a cyclic convolution feature is exploited to simplify the structure of the DA cells. Based on the proposed architecture, a real-time 65-point PFFT processor is designed, and the synthesis results show that it saves over 8% gates compared to the existing real-time 64-point DFT designs.
ER -
English
