An R-peak detection method with a high noise tolerance is presented in this paper. This method utilizes a customized deep convolution neural network (DCNN) to extract morphological and temporal features from sliced electrocardiogram (ECG) signals. The proposed network adopts multiple parallel dilated convolution layers to analyze features from diverse fields of view. A sliding window slices the original ECG signals into segments, and then the network calculates one segment at a time and outputs every point's probability of belonging to the R-peak regions. After a binarization and a deburring operation, the occurrence time of the R-peaks can be located. Experimental results based on the MIT-BIH database show that the R-peak detection accuracies can be significantly improved under high intensity of the electrode motion artifact or muscle artifact noise, which reveals a higher performance than state-of-the-art methods.

In dense passive radio frequency identification (RFID) systems, code division multiple access (CDMA) techniques can be used to alleviate severe collisions and thus enhance the system performance. However, conventional CDMA techniques are challenging to implement, especially for passive tags due to cost and power constraints. In this paper, we design a CDMA-based multi-reader passive ultra high frequency (UHF) RFID system in which a reader detects only the strongest tag signal and a tag uses Gold codes only on the preamble and the data bits of RN16 without increasing its clock frequency. We present a new communication procedure based on dynamic framed slotted ALOHA (DFSA). In order to optimize the system, we theoretically analyze the system performance in terms of slot capacity and identification rate, and formally show how the code length and the number of readers affect the identification rate. Furthermore, we propose an effective method for tag estimation and frame size adjustment, and validate it via simulations. Through an example, we demonstrate how the analysis-based technique can be used to optimize the system configurations with respect to the number of readers and the number and length of Gold codes.

The increasing complexity of embedded applications and the prevalence of multiprocessor system-on-chip (MPSoC) introduce a great challenge for designers on how to achieve performance and programmability simultaneously in embedded systems. Automatic multithreaded code generation methods taking account of performance optimization techniques can be an effective solution. In this paper, we consider the issue of increasing processor utilization and reducing communication cost during multithreaded code generation from Simulink models to improve system performance. We propose a combination of three-layered multithreaded software with Integer Linear Programming (ILP) based design-time mapping and scheduling policies to get optimal performance. The hierarchical software with a thread layer increases processor usage, while the mapping and scheduling policies formulate a group of integer linear programming formulations to minimize communication cost as well as to maximize performance. Experimental results demonstrate the advantages of the proposed techniques on performance improvements.