The search functionality is under construction.
The search functionality is under construction.

Author Search Result

[Author] Yasuo OHMORI(2hit)

1-2hit
  • A Study for the Design of a New Mechanism of Wire Dot Print Head

    Akinori WATANABE  Hirokazu ANDO  Yasuo OHMORI  

     
    PAPER-Components

      Vol:
    E65-E No:7
      Page(s):
    397-404

    The mechanisms of the conventional spring driving types of the wire dot print heads having been studied, a new mechanism is proposed. The new mechanism is designed on the principle of the center of percussion of a body, and has the merits of good characteristics and low cost. In order to design the new mechanism reasonably, the collision vibrations are analyzed by the wave equation. It is shown in the analysis that impact printing characteristics of the new mechanism are determined by three parameters: printing medium stiffness, armature stiffness and mass ratio of the armature to the wire. The design targets are also represented by these three parameters. The relation between the center of percussion and the center of rotation of the armature is clarified on a standpoint of the collision vibration. This analysis can be applied to various mechanisms of wire dot print heads. Calculated results agree with experimental results. The new mechanism was proved to be much better than that of the conventional leaf spring by experiments.

  • A Bipolar Divided Word-Line Scheme for a High-Speed and Large-Capacity BiCMOS SRAM

    Takakuni DOUSEKI  Tadashi NAGAYAMA  Yasuo OHMORI  

     
    PAPER

      Vol:
    E75-C No:11
      Page(s):
    1364-1368

    A divided work-line scheme which uses a bipolar current-switch circuit is proposed. This structures allows high-speed and low-power operation by reducing the logic swing in the long main word lines and decreasing the current in the nonselected decoder. Two key circuits, the bipolar main decoder and the section decoder, are described in detail. These circuits, with a bipolar two-level cascode current-swich circuit, enable the SRAM to operate on a low external supply voltage. To demonstrate the effectiveness of this concept, an ECL100K interface 256-kb SRAM is designed and fabricated using 0.8-µm BiCMOS technology. A typical address access time of 5.5 ns and the power consumption of 750 mW are obtained.