A Bipolar Divided Word-Line Scheme for a High-Speed and Large-Capacity BiCMOS SRAM
Summary :
A divided work-line scheme which uses a bipolar current-switch circuit is proposed. This structures allows high-speed and low-power operation by reducing the logic swing in the long main word lines and decreasing the current in the nonselected decoder. Two key circuits, the bipolar main decoder and the section decoder, are described in detail. These circuits, with a bipolar two-level cascode current-swich circuit, enable the SRAM to operate on a low external supply voltage. To demonstrate the effectiveness of this concept, an ECL100K interface 256-kb SRAM is designed and fabricated using 0.8-µm BiCMOS technology. A typical address access time of 5.5 ns and the power consumption of 750 mW are obtained.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.11 pp.1364-1368
- Publication Date
- 1992/11/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memories)
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Takakuni DOUSEKI, Tadashi NAGAYAMA, Yasuo OHMORI, "A Bipolar Divided Word-Line Scheme for a High-Speed and Large-Capacity BiCMOS SRAM" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 11, pp. 1364-1368, November 1992, doi: .
Abstract: A divided work-line scheme which uses a bipolar current-switch circuit is proposed. This structures allows high-speed and low-power operation by reducing the logic swing in the long main word lines and decreasing the current in the nonselected decoder. Two key circuits, the bipolar main decoder and the section decoder, are described in detail. These circuits, with a bipolar two-level cascode current-swich circuit, enable the SRAM to operate on a low external supply voltage. To demonstrate the effectiveness of this concept, an ECL100K interface 256-kb SRAM is designed and fabricated using 0.8-µm BiCMOS technology. A typical address access time of 5.5 ns and the power consumption of 750 mW are obtained.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_11_1364/_p
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@ARTICLE{e75-c_11_1364,
author={Takakuni DOUSEKI, Tadashi NAGAYAMA, Yasuo OHMORI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Bipolar Divided Word-Line Scheme for a High-Speed and Large-Capacity BiCMOS SRAM},
year={1992},
volume={E75-C},
number={11},
pages={1364-1368},
abstract={A divided work-line scheme which uses a bipolar current-switch circuit is proposed. This structures allows high-speed and low-power operation by reducing the logic swing in the long main word lines and decreasing the current in the nonselected decoder. Two key circuits, the bipolar main decoder and the section decoder, are described in detail. These circuits, with a bipolar two-level cascode current-swich circuit, enable the SRAM to operate on a low external supply voltage. To demonstrate the effectiveness of this concept, an ECL100K interface 256-kb SRAM is designed and fabricated using 0.8-µm BiCMOS technology. A typical address access time of 5.5 ns and the power consumption of 750 mW are obtained.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Bipolar Divided Word-Line Scheme for a High-Speed and Large-Capacity BiCMOS SRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 1364
EP - 1368
AU - Takakuni DOUSEKI
AU - Tadashi NAGAYAMA
AU - Yasuo OHMORI
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1992
AB - A divided work-line scheme which uses a bipolar current-switch circuit is proposed. This structures allows high-speed and low-power operation by reducing the logic swing in the long main word lines and decreasing the current in the nonselected decoder. Two key circuits, the bipolar main decoder and the section decoder, are described in detail. These circuits, with a bipolar two-level cascode current-swich circuit, enable the SRAM to operate on a low external supply voltage. To demonstrate the effectiveness of this concept, an ECL100K interface 256-kb SRAM is designed and fabricated using 0.8-µm BiCMOS technology. A typical address access time of 5.5 ns and the power consumption of 750 mW are obtained.
ER -
English
