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Kenichi OHHATA Takeshi KUSUNOKI Hiroaki NAMBU Kazuo KANETANI Keiichi HIGETA Kunihiko YAMAGUCHI Noriyuki HOMMA
We describe the design of ECL write circuits and a CMOS memory cell in an ECL-CMOS SRAM to achieve ultra-fast cycle time. Factors determining the write cycle are reduced by several novel circuit techniques and by optimizing the design of the write circuits and CMOS memory cell, thereby, enabling ultra-fast cycle time. Key techniques are a bit line overdriving, the use of an overshoot suppressing emitter follower and a WPG with a replica memory cell delayer. The 72-kb ECL-CMOS SRAM macro through which these techniques were implemented was fabricated using 0. 3-µm BiCMOS technology. The RAM macro achieves a short cycle time of 2 ns without sacrificing stable memory cell operation. These techniques thus provide SRAMs with a shorter cycle time in the cache memories of high performance computer systems.
Kenichi OHHATA Takeshi KUSUNOKI Hiroaki NAMBU Kazuo KANETANI Toru MASUDA Masayuki OHAYASHI Satomi HAMAMOTO Kunihiko YAMAGUCHI Youji IDEI Noriyuki HOMMA
A novel redundancy method suitable for an ultra-high-speed SRAM with logic gates is proposed. Fuse decoders are used to reduce the number of fuses, thus suppressing the access time degradation. This makes it possible to flip chip bond an SRAM with logic gates, which has a high pin count and operates at a very high frequency. To combine the new redundancy method and an ECL decoder circuit with a BiCMOS inverter, several schemes for disabling a defective cell and enabling a spare one are discussed. A 1-Mb ECL-CMOS SRAM with 120-k logic gates was fabricated using 0.3-µm BiCMOS technology. This SRAM consists of 16 RAM macros, and the RAM macro had an access time of only 0.65 ns. The access time degradation after repair was less than 50 ps.
Kenichi OHHATA Yoshiaki SAKURAI Hiroaki NAMBU Kazuo KANETANI Youji IDEI Toshirou HIRAMOTO Nobuo TAMBA Kunihiko YAMAGUCHI Masanori ODAKA Kunihiko WATANABE Takahide IKEDA Noriyuki HOMMA
An ECL-CMOS SRAM technology is proposed which features a combination of ECL word drivers, ECL write circuits and low-voltage CMOS cells. This technology assures both ultra-high-speed and high-density. In the ECL-CMOS SRAM,various kinds of noise generated during the write cycle seriously affect the memory performance, because it has much faster access than conventional SRAMs. To overcome this problem, we propose three noise reduction techniques; a noise reduction clamp circuit, an emitter follower with damping capacitor and a twisted bit line structure with "normally on" equalizer. These techniques allow fast accese and cycle times. To evaluate these techniques, a 64-kb SRAM chip was fabricated using 0.5-µm BiCMOS technology. This SRAM has a short cycle time of 2 ns and a very fast access time of 1.5 ns. Evaluation proves the usefulness of these techniques.
Takakuni DOUSEKI Tadashi NAGAYAMA Yasuo OHMORI
A divided work-line scheme which uses a bipolar current-switch circuit is proposed. This structures allows high-speed and low-power operation by reducing the logic swing in the long main word lines and decreasing the current in the nonselected decoder. Two key circuits, the bipolar main decoder and the section decoder, are described in detail. These circuits, with a bipolar two-level cascode current-swich circuit, enable the SRAM to operate on a low external supply voltage. To demonstrate the effectiveness of this concept, an ECL100K interface 256-kb SRAM is designed and fabricated using 0.8-µm BiCMOS technology. A typical address access time of 5.5 ns and the power consumption of 750 mW are obtained.