1-4hit |
Yasushi SHIZUKI Yumi FUCHIDA Fumio SASAKI Kazuhiro ARAI Shigeru WATANABE
A novel K-band MMIC frequency doubler has been developed using resistive series feedback circuit. The doubler exhibits much better D/U ratio, smaller output power variation against ambient temperature and lower power consumption than those of the conventional single-ended doubler. This paper presents the simulation results on the effect of the resistive series feedback by harmonic balance methods. To obtain practical and accurate simulation results, newly developed gate charge model for Cgs and Cgd is introduced. The fabricated result of the proposed MMIC is also demonstrated.
Yasushi SHIZUKI Shigeru WATANABE
Problems of flipped-chip MMIC at millimeter-wave frequency are investigated. Practical design criteria are introduced to obtain resonance and cutoff frequency for parasitic mode with flipped-chip MMIC structure. We investigate the advantages and disadvantages of three types of transmission line for flipped-chip MMIC in both electromagnetic simulation and scale-model. To avoid the resonance in coplanar waveguide flipped-chip MMIC new bridge structure is proposed.
Yasushi SHIZUKI Ken ONODERA Kazuhiro ARAI Masaaki ISHIDA Shigeru WATANABE
A K-band MMIC subharmonically pumped mixer integrating local oscillator (LO) amplifier has been developed. For up-converter application, it is necessary to reduce the leakage of second harmonic component of LO frequency to RF port, which is generated by nonlinear operation of LO amplifier. A quasi-lumped short-circuited stub using microstrip structure has been successfully applied to the MMIC mixer to enhance 2fLO-suppression. We propose a new configuration of a quasi-lumped short-circuited stub, which reduces the influence of parasitic elements of via-holes. The developed MMIC has a one-stage LO amplifier and it has shown about 10 dB-improvement of 2fLO-suppression compared to conventional configuration using a quarter-wavelength short-circuited stub.
Yasushi SHIZUKI Ken ONODERA Fumio SASAKI Kazuhiro ARAI Hiroyuki YOSHINAGA Juichi OZAKI
A compact MMIC power amplifier which delivers P1dB of 25.8 dBm (380 mW) at 40 GHz has been developed. To make the chip width narrower, only one unit block using two parallel HEMTs is applied for a power stage. For achieving broadband interstage matching when using wide gate-width unit devices in the power stage, a new configuration of a unit block which contains a shunt capacitance is proposed.