The advances in silicon IC technology have provided an incredible performance increase in MPU developments. This paper describes that history of microprocessor developments, as well as future direction of MPU developments from the viewpoint of architectural design. Also, an empirical study of the development shows that changes of MPU generation occurs every four years with rapid performance increase between generations.

In the mid-1990s, ULSI technology will reach Sub-Half-Micron Era and Si chips with 0.30.4 µm design rules will be in the market. The shrinked device size makes it possible to realize a device count of more than 107 and a logic speed of 100200 picosecond per gate. By taking full advantage of these advanced process and device technologies, three basic trends; i.e., (a) higher integration and higher performance, (b) "system-on-chip" or system incorporation onto a single chip, and (c) customization, will be accelerated. Memories will include more logic fuctions on a chip and will become system memories. Microprocessors and ASICs will find a wider variety of applications in data processing, in signal processing and in control. It is prospected definitely that ULSI architecture technology, including system technology and circuit technology, will become more and more important for the progress aiming at the sub-half-micron ULSIs. This paper describes the technology issues that are specific for ULSI memories, microprocessors and ASICs. It overviews technology issues that are common to various ULSI chips, covering design, test, fault-tolerant technique, packaging, and high-speed device circuit. A few of future technological issues, such as Cryo-CMOS/BiCMOS and neural network, are briefly discussed with regard to their potentials as the new elements in ULSI architecture.

At the beginning of the 21st century, 1 Gb DRAMs will be in practical use, and sufficient in terms of memory capacity for most memory applications systems. The key technologies for multimedia systems include data compression, communication, storage, and human interfaces. Image data processing, ATM switch, and microprocessor in multimedia applications require the high data transfer rate from several 100 Mbits/s to Tbits/s. Storage systems, on the other hand, require the reduction of the price per bit to less than 10 cents/Mbytes. Application specific design approaches towards a system-on-chip are strongly needed for ULSI memories in the multimedia era.

A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 µm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 mm7.1 mm die.