IEICE TRANSACTIONS on Electronics
A 0.9-V, 2.5 MHz CMOS 32-bit Microprocessor
Summary :
A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 µm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 mm
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E78-C No.4 pp.389-393
- Publication Date
- 1995/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
- Category
- Digital Circuits
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Hiroaki SUZUKI, Toshichika SAKAI, Hisao HARIGAI, Yoichi YANO, "A 0.9-V, 2.5 MHz CMOS 32-bit Microprocessor" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 4, pp. 389-393, April 1995, doi: .
Abstract: A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 µm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 mm
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_4_389/_p
Copy
@ARTICLE{e78-c_4_389,
author={Hiroaki SUZUKI, Toshichika SAKAI, Hisao HARIGAI, Yoichi YANO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 0.9-V, 2.5 MHz CMOS 32-bit Microprocessor},
year={1995},
volume={E78-C},
number={4},
pages={389-393},
abstract={A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 µm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 mm
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A 0.9-V, 2.5 MHz CMOS 32-bit Microprocessor
T2 - IEICE TRANSACTIONS on Electronics
SP - 389
EP - 393
AU - Hiroaki SUZUKI
AU - Toshichika SAKAI
AU - Hisao HARIGAI
AU - Yoichi YANO
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1995
AB - A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 µm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 mm
ER -
English
