This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSIs now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing: 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static cicuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.

With the development in portable electronic equipment, the demand for secondary batteries of high energy density is increasing. Recently, nickel metal hydride secondary batteries (Ni/MH) are expanding the market, and lithium ion secondary batteries have been newly developed and commercialized. This paper describes in detail Ni/MH and lithium ion secondary batteries, and reports on their development state and characteristics.

A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p⁺ buried layer and a low sheet-resistance extrinsic n⁺ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm². Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF₂-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.

We propose and fabricate n⁺-p⁺ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, dispite a low channel doping concentration of 10¹⁵ cm^-3, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19 µm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1 µm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.

We report the first monolithic integration of InGaAs/InAlAs resonant tunneling diode (RTD) and high electron mobility transistor (HEMT) epitaxially grown on an InP substrate. The transconductance for a 1-µm gate HEMT was 430 mS/mm and the peak-to-valley current ratio of the RTD was 5.1. Using the integrated structure, we demonstrate basic digital circuits to show low power characteristics of an RTD-load inverter and a static RAM cell circuit, consisting of a single transistor with two RTDs on the transistor. The memory cell circuit exhibits bistability, based on the RTD's negative differential resistance (NDR), at supply voltages from 0.6 to 1.1 V. The static power consumption was 7.3 µW/gate for the inverter and 3.0 µW for memory cell.

We propose a directly controlled emitter-follower circuit with a feedback type level stabilizer for low-voltage, low-power and high-speed bipolar ECL circuits. The emitter-follower circuit employs a current source structure that compensates speed and power for various supply voltage and temperature. The feedback controlled circuit with a small current source stabilizes 'High' level. At a power consumption of 1 mW/gate, the new circuit is 45% faster under the loaded condition (FO1, CL0.5 pF) and has 47% better load driving capability than conventional ECL gates.

A new approach which implements a simple, high-speed phase detector with precharge logic will be presented. The minimum detectable phase difference is 40 psec, which is less than a half of conventional detectors. A current mode ring oscillator with a complementary-input bias generator has also been developed to enhance the dynamic range of the VCO under a low supply voltage. A fully CMOS PLL was designed using 0.5-µm technology. By virtue of this simple, fast detector, the wide operation range of 250 MHz at 1.5 V to 622 MHz at 3.0 V was achieved by simulation.

A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 µm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 mm7.1 mm die.

A low power bus architecture with Local and Global Charge-Recycling Bus (Local-CRB and Global-CRB) techniques, featuring virtual stacking of the individual bus-capacitance and the dummy capacitor into a series configuration between supply voltage and ground, has been proposed. These Local and Global CRB schemes make it possible to reduce not only each bus-swing but also a total equivalent bus-capacitance of the ultra multi-bit buses running in parallel. The voltage swing of each bus is given by the recycled charge-supplying from the upper adjacent bus capacitance or the dummy capacitor, instead of the power line. The dramatical power reduction was verified by the simulated and measured data. According to these data, if employing the combination of those CRB schemes in a practical chip, the ultra-high data rate of 25 Gb/s can be achieved while maintaining the power dissipation to be less than 300 mW at V_cc3.6 V for the bus width of 512 bit with the bus-capacitance of 14 pF per bit operating at 50 MHz.

Two types of dynamic termination, latch-type and RC-type, are useful for low-power high-speed chip interconnection where the transmission line is terminated only if the signal is changed. The gate of the termination MOS in the latch-type is driven by a feedback inverter, and that in the RC-type is driven by a differentiating signal through the resistor and capacitor. The power dissipation is 13% for the latch-type, and 11% for the RC-type in a DC termination scheme, and the overshoot is 32% for the latch-type, and 16% for the RC-type in an open scheme, both at a signal amplitude of 2 V. The RC-type is superior for signal swing as low as a 1 V. On the other hand, RC termination requires large capacitance, and thus high power. Diode termination is not effective for a small swing because of the large ON voltage of diodes.

The state of the art of low-voltage (LV) analog circuit design techniques is reviewed, and fundamental design techniques are identified and classified as follows: 1) current-mode, 2) series-to-parallel, 3) signal range sharing, 4) dynamic bias, 5) linear bias, and 6) LV regulator. A relatively wide variety of low frequency application circuits have been developed, but future development is expected for wide-bandwidth application circuits such as a voltage-controlled-oscillator (VCO), a balanced multiplier, etc. The circuit techniques such as current-mode, signal range sharing, and dynamic bias will probably be most important for advanced future circuit designs.

A monolithic linear power amplifier IC operating with a single low 2.7-V supply has been developed for 1.9-GHz digital mobile communication systems, such as the Japanese personal handy phone system (PHS). Refractory WN_x/W self-aligned gate GaAs power MESFETs have been successfully developed for L-band power amplification, and this power amplifier operates with high efficiency and low distortion at a low voltage of 2.7 V, without any additional negative voltage supply, by virtue of small drain knee voltage, high transconductance and sufficient breakdown voltage of the power MESFET. An output power of 23.0 dBm and a high power-added efficiency of 30.8% were attained for 1.9-GHz π/4-shifted QPSK (quadrature phase shift keying) modulated input when adjacent channel leakage power level was less than -60 dBc at 600 kHz apart from 1.9 GHz.

Low-power technology for front-end GaAs ICs and hybrid IC (HIC) for a mobile communication equipment will be presented. For low-power operation of GaAs front-end ICs, new techniques of the intermediate tuned circuits, the single-ended mixer, dualgate MESFETs, and the asymmetric self-aligned LDD process were investigated. The designed down-converter IC showed conversion gain of 21 dB, noise figure of 3.5 dB, 3rd-order intercept point in output level (IP_3out) of 4.0 dBm, image-rejection ratio of 20 dB at 880 MHz, operating at 3.0 V of supply voltage and 5.0 mA of dissipation current. The down-converter IC was also designed for 1.9 GHz to obtain conversion gain of 20 dB, noise figure of 4.0 dB, IP_3out of 4.0 dBm, image-rejection ratio of 20 dB at 3.0 V, 5.0 mA. The up-converter IC was designed for 1.9 GHz using the same topology of circuit and showed conversion gain of 15 dB, IP_3out of 7.5 dBm, and 1 dB compression level of -8 dBm with -20 dBm of LO input power, operating at 3.0 V, 8.0 mA. Another approach to the low-power operation was carried out by HIC using the GaAs down-converter IC chip. The HIC was designed for 880 MHz to show conversion gain of 27 dB, noise figure of 3.3 dB, IP_3out of 3.0 dBm, image-rejection ratio of 12 dB, at 2.7 V, 4.5 mA. The HIC measures only 8.0 mm6.0 mm1.2 mm.

Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.

The paper ptoposes a method to synthesize low-power control-logic modules by combining transistor-size optimization and transistor layout. Transistor sizing and layout work synergistically to achieve power/area optimization. Transistor size minimization provides more spaces for layout to be compacted. Layout compaction results in shorter wire length (i.e. smaller load capacitance), which allows transistors to become smaller. The details of transistor sizing and layout compaction are also described. When applied to circuits with up to 10,000 transistors, the optimizer reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.

Device models for a laser diode, photodetector, MESFET, HEMT, bipolar transistor, diode, and resistor are proposed and are implemented in a commercial mixed-signal simulator along with models for an optical fiber, an external optical modulator, and a pulse pattern generator. The validity of the models is confirmed by comparing simulated and experimental results. The performance of a mixed photonic/electronic circuit, which is determined by a large-signal waveform and the device noises, is estimated by the present analysis method.

A self-induced-transparent (SIT) system that takes advantage of morphology dependent resonances (MDR's) in a Mie-sized microsphere doped with a resonant material is proposed. The present system is doubly resonant: one has microscopic origin (the two-level system), while the other has macroscopic origin (the MDR). In this geometry, owing to the feedback action of MDR's, the pulse area can be much expanded, and thus the electric-field amplitude of the incident pulse can be reduced substantially compared with the conventional one-way SIT propagation. Theoretical results that incorporate dephasing due to structural imperfections are shown.