High-Speed High-Density Self-Aligned PNP Technology for Low-Power Complementary Bipolar ULSIs

Katsuyoshi WASHIO; Hiromi SHIMAMOTO; Tohru NAKAMURA

High-Speed High-Density Self-Aligned PNP Technology for Low-Power Complementary Bipolar ULSIs

Katsuyoshi WASHIO, Hiromi SHIMAMOTO, Tohru NAKAMURA

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A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p⁺ buried layer and a low sheet-resistance extrinsic n⁺ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm². Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF₂-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.4 pp.353-359

Publication Date: 1995/04/25

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Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)

Category: Device Technology

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Katsuyoshi WASHIO, Hiromi SHIMAMOTO, Tohru NAKAMURA, "High-Speed High-Density Self-Aligned PNP Technology for Low-Power Complementary Bipolar ULSIs" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 4, pp. 353-359, April 1995, doi: .
Abstract: A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p⁺ buried layer and a low sheet-resistance extrinsic n⁺ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm². Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF₂-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_4_353/_p

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@ARTICLE{e78-c_4_353,
author={Katsuyoshi WASHIO, Hiromi SHIMAMOTO, Tohru NAKAMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Speed High-Density Self-Aligned PNP Technology for Low-Power Complementary Bipolar ULSIs},
year={1995},
volume={E78-C},
number={4},
pages={353-359},
abstract={A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p⁺ buried layer and a low sheet-resistance extrinsic n⁺ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm². Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF₂-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - High-Speed High-Density Self-Aligned PNP Technology for Low-Power Complementary Bipolar ULSIs
T2 - IEICE TRANSACTIONS on Electronics
SP - 353
EP - 359
AU - Katsuyoshi WASHIO
AU - Hiromi SHIMAMOTO
AU - Tohru NAKAMURA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1995
AB - A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p⁺ buried layer and a low sheet-resistance extrinsic n⁺ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm². Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF₂-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.
ER -