IEICE TRANSACTIONS on Electronics
A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability
Summary :
Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E78-C No.4 pp.436-440
- Publication Date
- 1995/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
- Category
- DA/Architecture
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Kunihiro ASADA, Junichi AKITA, "A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 4, pp. 436-440, April 1995, doi: .
Abstract: Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_4_436/_p
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@ARTICLE{e78-c_4_436,
author={Kunihiro ASADA, Junichi AKITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability},
year={1995},
volume={E78-C},
number={4},
pages={436-440},
abstract={Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability
T2 - IEICE TRANSACTIONS on Electronics
SP - 436
EP - 440
AU - Kunihiro ASADA
AU - Junichi AKITA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1995
AB - Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.
ER -
English
