High-Speed and Low-Power n+-p+ Double-Gate SOI CMOS
Summary :
We propose and fabricate n+-p+ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, dispite a low channel doping concentration of 1015 cm-3, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19 µm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1 µm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E78-C No.4 pp.360-367
- Publication Date
- 1995/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
- Category
- Device Technology
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Kunihiro SUZUKI, Tetsu TANAKA, Yoshiharu TOSAKA, Hiroshi HORIE, Toshihiro SUGII, "High-Speed and Low-Power n+-p+ Double-Gate SOI CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 4, pp. 360-367, April 1995, doi: .
Abstract: We propose and fabricate n+-p+ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, dispite a low channel doping concentration of 1015 cm-3, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19 µm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1 µm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_4_360/_p
Copy
@ARTICLE{e78-c_4_360,
author={Kunihiro SUZUKI, Tetsu TANAKA, Yoshiharu TOSAKA, Hiroshi HORIE, Toshihiro SUGII, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Speed and Low-Power n+-p+ Double-Gate SOI CMOS},
year={1995},
volume={E78-C},
number={4},
pages={360-367},
abstract={We propose and fabricate n+-p+ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, dispite a low channel doping concentration of 1015 cm-3, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19 µm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1 µm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - High-Speed and Low-Power n+-p+ Double-Gate SOI CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 360
EP - 367
AU - Kunihiro SUZUKI
AU - Tetsu TANAKA
AU - Yoshiharu TOSAKA
AU - Hiroshi HORIE
AU - Toshihiro SUGII
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1995
AB - We propose and fabricate n+-p+ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, dispite a low channel doping concentration of 1015 cm-3, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19 µm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1 µm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.
ER -
English
