Theoretical and experimental evaluations of the horizontal rotating and tilting of the base station antenna beam show that these techniques are effective in reducing delay spread. Result show good agreement between predicted and measured values.

Dynamic Threshold-Voltage MOSFETs (DTMOS) in which the body is connected to the gate provide extremely high transconductance for supply voltages as low as under 0.7 V. This is because the forward body-source bias lowers the threshold voltage, which results in large gate drive and large drain current. This paper describes the high frequency characteristics of DTMOS for the first time. The DTMOS we analyzed has a small parasitic resistance due to employing optimized Co salicide technology. It also has a small parasitic capacitance due to a reduction in the overlapping region between the gate and drain, which is achieved by employing gate poly-Si oxidation prior to LDD implantation. We obtained an Ft of 78 GHz and an Fmax of 37 GHz for a 0. 1-µm-Leff DTMOS even at a supply voltage of 0.7 V. We also observed an Fmax enhancement by 1.5 times for a 0.12-µm-Leff DTMOS compared to a conventional SOI MOSFET, which we attributed to high transconductance and large output resistance. The DTMOS can be considered as the most promising device for low-power RF LSIs.

We propose and fabricate n+-p+ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, dispite a low channel doping concentration of 1015 cm-3, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19 µm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1 µm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.