A comprehensive model is presented for estimating the bit error rate (BER) of write disturbance in a resistive memory composed of a cross-point array. While writing a datum into the selected address, the non-selected addresses are biased by word-line (WL) and bit-line (BL). The stored datum in the non-selected addresses will be disturbed if the bias is large enough. It is necessary for the current flowing through the non-selected address to be calculated in order to estimate the BER of the write disturbance. Since it takes a long time to calculate the current flowing in a large-scale cross-point array, several simplified circuits have been utilized to decrease the calculating time. However, these simplified circuits are available to the selected address, not to the non-selected one. In this paper, new simplified circuits are proposed for calculating the current flowing through the non-selected address. The proposed and the conventional simplified circuits are used, and on that basis the trade-off between the write disturbance and the write error is discussed. Furthermore, the error correcting code (ECC) is introduced to improve the trade-off and to provide the low-cost memory chip matching current production lines.

This paper describes fault-tolerant designs, which have been used to boost the yield of a 286 mm2 256 Mb DRAM with 32 both-ends DQ. The 256 Mb DRAM consists of sixteen 16 Mb units, each containing one 128 Kb row redundancy block. This row redundancy block architecture allows flexible row redundancy replacement, where random faults, clustered faults, and grouped faults can be efficiently repaired. Flexible column redundancy replacement with interchangeable master DQ's(MDQ) is used to allow a 256 b data compression without causing a data conflict, while improving the column access speed by 2 ns. A depletion NMOS bitline-precharge-current-limiter suppresses the current flow which occursas a result of a wordlinebitline short-circuit to only 15 µA per cross fail, avoiding a standby current fail. Consequently, the hardware results show a significant yield enhancement of 16 times relative to the intrablock/segment replacement. Detailed simulation results show that this 256 Mb DRAM allows 275 random faults to be repaired with 5.5% silicon area overhead for 80% chip yield.

A simplified circuit has been utilized for fast computation of the current flowing in the cross-point memory array. However, the circuit has a constraint in that the selected cell is located farthest from current drivers so as to estimate the current degraded by metal wire resistance. This is because the length of the current path along the metal wire varies with the selected address in the cross-point memory array. In this paper, a new simplified circuit is proposed for calculating the current at every address in order to take account of the metal wire resistance. By employing the Monte Carlo simulation to solve the proposed simplified circuit, the current distribution across the array is obtained, so that failure rates of read disturbance and write error are estimated precisely. By comparing the conventional and the proposed simplified circuits, it was found that the conventional simplified circuit estimated optimistic failure rates for read disturbance and for write error when the wire resistance was prominent enough as a parasitic resistance.