IEICE TRANSACTIONS on Electronics
A Comprehensive Model for Write Disturbance in Resistive Memory Composed of Cross-Point Array
Summary :
A comprehensive model is presented for estimating the bit error rate (BER) of write disturbance in a resistive memory composed of a cross-point array. While writing a datum into the selected address, the non-selected addresses are biased by word-line (WL) and bit-line (BL). The stored datum in the non-selected addresses will be disturbed if the bias is large enough. It is necessary for the current flowing through the non-selected address to be calculated in order to estimate the BER of the write disturbance. Since it takes a long time to calculate the current flowing in a large-scale cross-point array, several simplified circuits have been utilized to decrease the calculating time. However, these simplified circuits are available to the selected address, not to the non-selected one. In this paper, new simplified circuits are proposed for calculating the current flowing through the non-selected address. The proposed and the conventional simplified circuits are used, and on that basis the trade-off between the write disturbance and the write error is discussed. Furthermore, the error correcting code (ECC) is introduced to improve the trade-off and to provide the low-cost memory chip matching current production lines.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E100-C No.3 pp.329-339
- Publication Date
- 2017/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E100.C.329
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Yoshiaki ASAO
Toshiba
Fumio HORIGUCHI
Toyo University
Keyword
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Yoshiaki ASAO, Fumio HORIGUCHI, "A Comprehensive Model for Write Disturbance in Resistive Memory Composed of Cross-Point Array" in IEICE TRANSACTIONS on Electronics,
vol. E100-C, no. 3, pp. 329-339, March 2017, doi: 10.1587/transele.E100.C.329.
Abstract: A comprehensive model is presented for estimating the bit error rate (BER) of write disturbance in a resistive memory composed of a cross-point array. While writing a datum into the selected address, the non-selected addresses are biased by word-line (WL) and bit-line (BL). The stored datum in the non-selected addresses will be disturbed if the bias is large enough. It is necessary for the current flowing through the non-selected address to be calculated in order to estimate the BER of the write disturbance. Since it takes a long time to calculate the current flowing in a large-scale cross-point array, several simplified circuits have been utilized to decrease the calculating time. However, these simplified circuits are available to the selected address, not to the non-selected one. In this paper, new simplified circuits are proposed for calculating the current flowing through the non-selected address. The proposed and the conventional simplified circuits are used, and on that basis the trade-off between the write disturbance and the write error is discussed. Furthermore, the error correcting code (ECC) is introduced to improve the trade-off and to provide the low-cost memory chip matching current production lines.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.329/_p
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@ARTICLE{e100-c_3_329,
author={Yoshiaki ASAO, Fumio HORIGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Comprehensive Model for Write Disturbance in Resistive Memory Composed of Cross-Point Array},
year={2017},
volume={E100-C},
number={3},
pages={329-339},
abstract={A comprehensive model is presented for estimating the bit error rate (BER) of write disturbance in a resistive memory composed of a cross-point array. While writing a datum into the selected address, the non-selected addresses are biased by word-line (WL) and bit-line (BL). The stored datum in the non-selected addresses will be disturbed if the bias is large enough. It is necessary for the current flowing through the non-selected address to be calculated in order to estimate the BER of the write disturbance. Since it takes a long time to calculate the current flowing in a large-scale cross-point array, several simplified circuits have been utilized to decrease the calculating time. However, these simplified circuits are available to the selected address, not to the non-selected one. In this paper, new simplified circuits are proposed for calculating the current flowing through the non-selected address. The proposed and the conventional simplified circuits are used, and on that basis the trade-off between the write disturbance and the write error is discussed. Furthermore, the error correcting code (ECC) is introduced to improve the trade-off and to provide the low-cost memory chip matching current production lines.},
keywords={},
doi={10.1587/transele.E100.C.329},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - A Comprehensive Model for Write Disturbance in Resistive Memory Composed of Cross-Point Array
T2 - IEICE TRANSACTIONS on Electronics
SP - 329
EP - 339
AU - Yoshiaki ASAO
AU - Fumio HORIGUCHI
PY - 2017
DO - 10.1587/transele.E100.C.329
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2017
AB - A comprehensive model is presented for estimating the bit error rate (BER) of write disturbance in a resistive memory composed of a cross-point array. While writing a datum into the selected address, the non-selected addresses are biased by word-line (WL) and bit-line (BL). The stored datum in the non-selected addresses will be disturbed if the bias is large enough. It is necessary for the current flowing through the non-selected address to be calculated in order to estimate the BER of the write disturbance. Since it takes a long time to calculate the current flowing in a large-scale cross-point array, several simplified circuits have been utilized to decrease the calculating time. However, these simplified circuits are available to the selected address, not to the non-selected one. In this paper, new simplified circuits are proposed for calculating the current flowing through the non-selected address. The proposed and the conventional simplified circuits are used, and on that basis the trade-off between the write disturbance and the write error is discussed. Furthermore, the error correcting code (ECC) is introduced to improve the trade-off and to provide the low-cost memory chip matching current production lines.
ER -
English
