One of the bottlenecks for the efficient parallel processing is the communication overheads among resources. To solve this problem, we have been developing a high speed optical communication bus, which consists of laser diodes for signal emission, APDs for signal reception and a cylindrical mirror for broadcasting. The experimental system reported here operates at the clock frequency of 50 MHz.

A multi-chip superconducting computer named ETL-JC1 has been constructed based on Josephson computer technology developed in the Electrotechnical Laboratory through 1980s. The technology covers various fields such as material and fabrication technology, logic and memory circuit design, and computer archtecture. Some key technologies for making the ETL-JC1 have been developed; niobium (Nb) tunnel junction integration process, LSI logic circuits, memory chips of a 1-kbit ROM and a 1-kbit RAM, the CAD system for Josephson LSI design, and a multi-phase power supply system. The computer system was totally designed by the RISC (reduced instruction set computer) architecture. It consists of four Josephson LSI chips of an arithmetic/logic unit, a sequence control unit, a program memory unit, and a data memory unit, which are essential to execute computer functions. The four chips were fabricated with a 3-µm Nb/Al-oxide/Nb junction integration technology. The ETL-JC1 was constructed by connecting four Josephson LSI chips on a non-magnetic printed circuit board. Test programs were executed on the ETL-JC1 and the correct execution of all the 27 kinds of instruction including memory access, subroutine call/return, and so on, which are sufficient to make and computer program, was confirmed. A total power dissipation was 6.2 mW in whole circuits of the ETL-JC1 consisting of more than 22,000 Josephson junctions. Operation speed of 1 GIPS (Giga-instruction per second) can be expected with a single CPU in this system according to computer logic simulations.