Josephson Computer Technology for a Multi-Chip Computer ETL-JC1

Susumu TAKADA; Itaru KUROSAWA; Hiroshi NAKAGAWA; Masahiro AOYAGI; Shin KOSAKA; Youich HAMAZAKI; Yoshikuni OKADA

Josephson Computer Technology for a Multi-Chip Computer ETL-JC1

Susumu TAKADA, Itaru KUROSAWA, Hiroshi NAKAGAWA, Masahiro AOYAGI, Shin KOSAKA, Youich HAMAZAKI, Yoshikuni OKADA

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A multi-chip superconducting computer named ETL-JC1 has been constructed based on Josephson computer technology developed in the Electrotechnical Laboratory through 1980s. The technology covers various fields such as material and fabrication technology, logic and memory circuit design, and computer archtecture. Some key technologies for making the ETL-JC1 have been developed; niobium (Nb) tunnel junction integration process, LSI logic circuits, memory chips of a 1-kbit ROM and a 1-kbit RAM, the CAD system for Josephson LSI design, and a multi-phase power supply system. The computer system was totally designed by the RISC (reduced instruction set computer) architecture. It consists of four Josephson LSI chips of an arithmetic/logic unit, a sequence control unit, a program memory unit, and a data memory unit, which are essential to execute computer functions. The four chips were fabricated with a 3-µm Nb/Al-oxide/Nb junction integration technology. The ETL-JC1 was constructed by connecting four Josephson LSI chips on a non-magnetic printed circuit board. Test programs were executed on the ETL-JC1 and the correct execution of all the 27 kinds of instruction including memory access, subroutine call/return, and so on, which are sufficient to make and computer program, was confirmed. A total power dissipation was 6.2 mW in whole circuits of the ETL-JC1 consisting of more than 22,000 Josephson junctions. Operation speed of 1 GIPS (Giga-instruction per second) can be expected with a single CPU in this system according to computer logic simulations.

Publication: IEICE TRANSACTIONS on Electronics Vol.E74-C No.3 pp.568-577

Publication Date: 1991/03/25

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Susumu TAKADA
Itaru KUROSAWA
Hiroshi NAKAGAWA
Masahiro AOYAGI
Shin KOSAKA
Youich HAMAZAKI
Yoshikuni OKADA

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Susumu TAKADA, Itaru KUROSAWA, Hiroshi NAKAGAWA, Masahiro AOYAGI, Shin KOSAKA, Youich HAMAZAKI, Yoshikuni OKADA, "Josephson Computer Technology for a Multi-Chip Computer ETL-JC1" in IEICE TRANSACTIONS on Electronics, vol. E74-C, no. 3, pp. 568-577, March 1991, doi: .
Abstract: A multi-chip superconducting computer named ETL-JC1 has been constructed based on Josephson computer technology developed in the Electrotechnical Laboratory through 1980s. The technology covers various fields such as material and fabrication technology, logic and memory circuit design, and computer archtecture. Some key technologies for making the ETL-JC1 have been developed; niobium (Nb) tunnel junction integration process, LSI logic circuits, memory chips of a 1-kbit ROM and a 1-kbit RAM, the CAD system for Josephson LSI design, and a multi-phase power supply system. The computer system was totally designed by the RISC (reduced instruction set computer) architecture. It consists of four Josephson LSI chips of an arithmetic/logic unit, a sequence control unit, a program memory unit, and a data memory unit, which are essential to execute computer functions. The four chips were fabricated with a 3-µm Nb/Al-oxide/Nb junction integration technology. The ETL-JC1 was constructed by connecting four Josephson LSI chips on a non-magnetic printed circuit board. Test programs were executed on the ETL-JC1 and the correct execution of all the 27 kinds of instruction including memory access, subroutine call/return, and so on, which are sufficient to make and computer program, was confirmed. A total power dissipation was 6.2 mW in whole circuits of the ETL-JC1 consisting of more than 22,000 Josephson junctions. Operation speed of 1 GIPS (Giga-instruction per second) can be expected with a single CPU in this system according to computer logic simulations.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_3_568/_p

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@ARTICLE{e74-c_3_568,
author={Susumu TAKADA, Itaru KUROSAWA, Hiroshi NAKAGAWA, Masahiro AOYAGI, Shin KOSAKA, Youich HAMAZAKI, Yoshikuni OKADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Josephson Computer Technology for a Multi-Chip Computer ETL-JC1},
year={1991},
volume={E74-C},
number={3},
pages={568-577},
abstract={A multi-chip superconducting computer named ETL-JC1 has been constructed based on Josephson computer technology developed in the Electrotechnical Laboratory through 1980s. The technology covers various fields such as material and fabrication technology, logic and memory circuit design, and computer archtecture. Some key technologies for making the ETL-JC1 have been developed; niobium (Nb) tunnel junction integration process, LSI logic circuits, memory chips of a 1-kbit ROM and a 1-kbit RAM, the CAD system for Josephson LSI design, and a multi-phase power supply system. The computer system was totally designed by the RISC (reduced instruction set computer) architecture. It consists of four Josephson LSI chips of an arithmetic/logic unit, a sequence control unit, a program memory unit, and a data memory unit, which are essential to execute computer functions. The four chips were fabricated with a 3-µm Nb/Al-oxide/Nb junction integration technology. The ETL-JC1 was constructed by connecting four Josephson LSI chips on a non-magnetic printed circuit board. Test programs were executed on the ETL-JC1 and the correct execution of all the 27 kinds of instruction including memory access, subroutine call/return, and so on, which are sufficient to make and computer program, was confirmed. A total power dissipation was 6.2 mW in whole circuits of the ETL-JC1 consisting of more than 22,000 Josephson junctions. Operation speed of 1 GIPS (Giga-instruction per second) can be expected with a single CPU in this system according to computer logic simulations.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - Josephson Computer Technology for a Multi-Chip Computer ETL-JC1
T2 - IEICE TRANSACTIONS on Electronics
SP - 568
EP - 577
AU - Susumu TAKADA
AU - Itaru KUROSAWA
AU - Hiroshi NAKAGAWA
AU - Masahiro AOYAGI
AU - Shin KOSAKA
AU - Youich HAMAZAKI
AU - Yoshikuni OKADA
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1991
AB - A multi-chip superconducting computer named ETL-JC1 has been constructed based on Josephson computer technology developed in the Electrotechnical Laboratory through 1980s. The technology covers various fields such as material and fabrication technology, logic and memory circuit design, and computer archtecture. Some key technologies for making the ETL-JC1 have been developed; niobium (Nb) tunnel junction integration process, LSI logic circuits, memory chips of a 1-kbit ROM and a 1-kbit RAM, the CAD system for Josephson LSI design, and a multi-phase power supply system. The computer system was totally designed by the RISC (reduced instruction set computer) architecture. It consists of four Josephson LSI chips of an arithmetic/logic unit, a sequence control unit, a program memory unit, and a data memory unit, which are essential to execute computer functions. The four chips were fabricated with a 3-µm Nb/Al-oxide/Nb junction integration technology. The ETL-JC1 was constructed by connecting four Josephson LSI chips on a non-magnetic printed circuit board. Test programs were executed on the ETL-JC1 and the correct execution of all the 27 kinds of instruction including memory access, subroutine call/return, and so on, which are sufficient to make and computer program, was confirmed. A total power dissipation was 6.2 mW in whole circuits of the ETL-JC1 consisting of more than 22,000 Josephson junctions. Operation speed of 1 GIPS (Giga-instruction per second) can be expected with a single CPU in this system according to computer logic simulations.
ER -