The application of 3D-LSIs for character recognition image sensing processors in described. Three-dimensional LSIs will achieve very high performance by exploiting the structural parallelism by way of the inherence parallelism of an algorithm. As the first step, the three-story structured image sensing processor was implemented integrating 210 pixel photodiodes and 10.4 thousand transistors on a 5.04 mm 11.20 mm die. It is able to sense 6 characters of image at the same time and recognize 64 kind of characters, those are alphabet in capital and lower case, Arabic numerals and some symbols, each consists of 5 7 bit matrix. A four-story structured image sensing processor, which is the second step for realizing the advanced image sensor, integrating 5040 pixel photodiodes and 0.22 million transistors on a 14.3 mm square single die is currently under implementation. The present chip allows 20 times larger degree of data parallelism and several 10 times higher speed of data matching than the previous chip. And some other advantages have been achieved in its functions. Before the implementation of the present chip, its test element circuits were fabricated successively and the functions of the circuit blocks were confirmed. Each floor of 0.6 µm thick SOI film was recrystallized with Ar laser irradiation by the M-shaped beam method with parallel groove structure. The grain boundaries and defects are confined within each ridge region and the defect free single crystal Si film, whose crystal orientation is aligned to the (100) silicon on the lower floor, is grown on each groove region. The maximum temperature of atmosphere during fabrication process was 900. Both chips are made of a number of simple processing elements working in parallel to speed up a computation. So far only several floors can be fabricated as a single die. However the technology has been steadily progressing. The real "intelligent" image sensing processor will be implemented in the near future with 3D integration technology.

Most peer-to-peer (P2P) systems build their own overlay networks for implementing peer selection strategies without taking into account the locality on the underlay network. As a result, a large quantity of traffic crossing internet service providers (ISPs) or autonomous systems (ASes) is generated on the Internet. Controlling the P2P traffic is therefore becoming a big challenge for the ISPs. To control the cost of the cross-ISP/AS traffic, ISPs often throttle and/or even block P2P applications in their networks. In this paper, we propose a router-aided approach for localizing the P2P traffic hierarchically; it features the insertion of additional delay into each P2P packet based on geographical location of its destination. Compared to the existing approaches that solve the problem on the application layer, our proposed method does not require dedicated servers, cooperation between ISPs and P2P users, or modification of existing P2P application software. Therefore, the proposal can be easily utilized by all types of P2P applications. Experiments on P2P streaming applications indicate that our hierarchical traffic localization method not only reduces significantly the inter-domain traffic but also maintains a good performance of P2P applications.