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[Author] Zhichuan GUO(2hit)

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  • High Performance Network Virtualization Architecture on FPGA SmartNIC

    Ke WANG  Yiwei CHANG  Zhichuan GUO  

     
    PAPER-Network System

      Pubricized:
    2022/11/29
      Vol:
    E106-B No:6
      Page(s):
    500-508

    Network Functional Virtualization (NFV) is a high-performance network interconnection technology that allows access to traditional network transport devices through virtual network links. It is widely used in cloud computing and other high-concurrent access environments. However, there is a long delay in the introduction of software NFV solutions. Other hardware I/O virtualization solutions don't scale very well. Therefore, this paper proposes a virtualization implementation method on 100Gbps high-speed Field Programmable Gate Array (FPGA) network accelerator card, which uses FPGA accelerator to improve the performance of virtual network devices. This method uses the single root I/O virtualization (SR-IOV) technology to allow 256 virtual links to be created for a single Peripheral Component Interconnect express (PCIe) device. And it supports data transfer with virtual machine (VM) in the way of Peripheral Component Interconnect (PCI) passthrough. In addition, the design also adopts the shared extensible queue management mechanism, which supports the flexible allocation of more than 10,000 queues on virtual machines, and ensures the good isolation performance in the data path and control path. The design provides high-bandwidth transmission performance of more than 90Gbps for the entire network system, meeting the performance requirements of hyperscale cloud computing clusters.

  • High-Throughput Exact Matching Implementation on FPGA with Shared Rule Tables among Parallel Pipelines Open Access

    Xiaoyong SONG  Zhichuan GUO  Xinshuo WANG  Mangu SONG  

     
    PAPER-Network System

      Vol:
    E107-B No:5
      Page(s):
    387-397

    In software defined network (SDN), packet processing is commonly implemented using match-action model, where packets are processed based on matched actions in match action table. Due to the limited FPGA on-board resources, it is an important challenge to achieve large-scale high throughput based on exact matching (EM), while solving hash conflicts and out-of-order problems. To address these issues, this study proposed an FPGA-based EM table that leverages shared rule tables across multiple pipelines to eliminate memory replication and enhance overall throughput. An out-of-order reordering function is used to ensure packet sequencing within the pipelines. Moreover, to handle collisions and increase load factor of hash table, multiple hash table blocks are combined and an auxiliary CAM-based EM table is integrated in each pipeline. To the best of our knowledge, this is the first time that the proposed design considers the recovery of out-of-order operations in multi-channel EM table for high-speed network packets processing application. Furthermore, it is implemented on Xilinx Alveo U250 field programmable gate arrays, which has a million rules and achieves a processing speed of 200 million operations per second, theoretically enabling throughput exceeding 100 Gbps for 64-Byte size packets.