In Internet of Things (IoT) applications, system-on-chip (SoCs) with embedded processors are widely used. As an embedded processor, RISC-V, which is license-free and has an extensible instruction set, is receiving attention. However, designing such embedded processors requires an enormous effort to achieve a highly efficient microarchitecture in terms of performance, power consumption, and circuit area, as well as the design verification of running complex software, including modern operating systems such as Linux. In this paper, we propose a method for directly describing the RTL structure of a pipelined RISC-V processor with cache memories, a memory management unit (MMU), and an AXI bus interface using the C++ language. This pipelined processor C++ model serves as a functional simulator of the complete RISC-V core, whereas our C2RTL framework translates the processor C++ model into a cycle-accurate RTL description in the Verilog-HDL and RTL-equivalent C model. Our processor design methodology using the C2RTL framework is unique compared to other existing methodologies because both the simulation and RTL models are derived from the same C++ source, which greatly simplifies the design verification and optimization processes. The effectiveness of our design methodology is demonstrated on a RISC-V processor that runs Linux OS on an FPGA board, achieving a significantly short simulation time of the original C++ processor model and RTL-equivalent C model in comparison to a commercial RTL simulator.

Build systems are essential tools for developing large software projects. Traditionally, build systems have been designed for high incremental-build performance. However, the longer build times of recent large C++ projects have imposed a requirement on build systems: i.e., unity builds. Unity builds are a build technique for speeding up sequential compilation of many source files by bundling multiple source files into one. Unity builds lead to a significant reduction in build time through removal of redundant parsing of shared header files. However, unity builds have a negative effect on incremental builds because each compiler task gets larger. Our previous study reported existing unity builds overlook many better bundle configurations that improve unity-build performance without increasing the incremental-build time. Motivated by the problem, we present a novel build system for better performance in unity builds. Our build system aims to achieve competitive unity-build performance in full builds with mitigating the negative effect on incremental builds. To accomplish this goal, our build system uses sophisticated bundle strategies developed on the basis of hints extracted from the preprocessed code of each source file. Thanks to the strategies, our build system finds better bundle configurations that improve both of the full-build performance and the incremental-build performance in unity builds. For example, in comparison with the state-of-the-art unity builds of WebKit, our build system improves build performance by 9% in full builds, by 39% in incremental builds, and by 23% in continuous builds that include both types of the builds.

Timing verification of digital synchronous designs is a complex process that is traditionally carried out deep in the design cycle, at the gate level. A method, embodied in a C++ based design system, is presented that allows modeling and verification of clock regions at a higher level. By combining event-driven, clock-cycle true and behavioral simulation, we are able to perform static and dynamic timing analysis of the clock regions.

This letter empirically evaluates the way how to calculate the complexity of methods, that is used in the definition of WMC(Weighted Method per Class), one of the Chidamber and Kemerer's metrics. With respect to the results of our experiment, Halstead's Software Science metric is the most appropriate one to evaluate the complexity of the methods.

This paper presents a layered hierarchical switching-software technology, which is based on an object-oriented design approach, that improves software reusability and productivity. This technology enables a non-stop, service-enhanceable software environment (called NOSES), which satisfies customer demands for quick provisioning of new service features without interrupting service, and which improves software reliability. This technology was developed as part of our overall plan to establish a communications software platform that can be customized for use by various communications systems, such as STM, ATM, and IN. The developed non-stop service enhanceable software techniques are call-recovery restart, system file update, and on-line partial file modification; they were achieved by using dynamic program modification. A system file update inevitably affects calls in service, despite efforts to save in-service calls by copying the call data from the old file to the new one. We have therefore developed a different approach: on-line partial-file modification. Our prototype switching system has proven the effectiveness of this modification method and has shown that it can cover a limited range of service feature additions (which meets customer demands for quick service provisioning), as well as all bug fixes (which can lead to higher software reliability due to not using conventional machine code for software patching), without interrupting service. This paper describes on-line partial-file modification, which can be applied to communications systems that require resident program modification or initialization without program loading; that is, the program exists permanently in main memory. An evaluation of this approach also showed that the productivity of service-layer software increases about two times and that the total increase in systems development productivity is about 25%.