HEMT comparators for ultrahigh-speed A/D converters have been investigated. In particular, the transition times of the D-latch used in the comparator have been analyzed by assuming a 0.1-µm HEMT technology. It is found that for small input signals (<0.1 V), the transition time from the track to latch phase dominates the comparator operation speed. As the input signal increases, this time decreases due to the positive feedback in the latch, and the comparator speed is limited by the transition time from the latch to track phase. The transition times of 20 ps have been estimated for the present comparator.

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ED by 45.5% over ep-SFF. The simulations were performed in a 0.1 µm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.