With the development of IoT devices and sensors, edge computing is leading towards new services like autonomous cars and smart cities. Low-latency data access is an essential requirement for such services, and a large-capacity cache server is needed on the edge side. However, it is not realistic to build a large capacity cache server using only DRAM because DRAM is expensive and consumes substantially large power. A hybrid main memory system is promising to address this issue, in which main memory consists of DRAM and non-volatile memory. It achieves a large capacity of main memory within the power supply capabilities of current servers. In this paper, we propose Fogcached, that is, the extension of a widely-used KVS (Key-Value Store) server program (i.e., Memcached) to exploit both DRAM and non-volatile main memory (NVMM). We used Intel Optane DCPM as NVMM for its prototype. Fogcached implements a Dual-LRU (Least Recently Used) mechanism that seamlessly extends the memory management of Memcached to hybrid main memory. Fogcached reuses the segmented LRU of Memcached to manage cached objects in DRAM, adds another segmented LRU for those in DCPM and bridges the LRUs by a mechanism to automatically replace cached objects between DRAM and DCPM. Cached objects are autonomously moved between the two memory devices according to their access frequencies. Through experiments, we confirmed that Fogcached improved the peak value of a latency distribution by about 40% compared to Memcached.

In this prompt report, we present the basic performance evaluation of Intel Optane Data Center Persistent Memory Module (Optane DCPMM), which is the first commercially-available, byte-addressable non-volatile memory modules released in April 2019. Since at the moment of writing only a few reports on its performance were published, this letter is intended to complement other performance studies. Through experiments using our own measurement tools, we obtained that the latency of random read-only access was approximately 374 ns. That of random writeback-involving access was 391 ns. The bandwidths of read-only and writeback-involving access for interleaved memory modules were approximately 38 GB/s and 3 GB/s, respectively.

This paper presents an image haze removal algorithm for a single image. The conventional Dark Channel Prior (DCP) algorithm estimates the transmission map using the dark information in an image. The haze regions are then detected using a matting algorithm. However, the resulting transmission map invariably includes some block artifacts as the DCP algorithm is based on block-based processing. Therefore, to solve this problem, an algorithm for a modified transmission map is proposed using a Hidden Markov Random Field (HMRF) algorithm. Experimental results confirm that the proposed algorithm is superior to conventional algorithms in image haze removal.

This paper compares the turbo code and rate-compatible low-density parity-check (LDPC) codes based on the block error rate (BLER) performance and decoding complexity in order to clarify which channel coding scheme is most appropriate for the channel coding scheme in the OFDM based Evolved UTRA (E-UTRA) downlink. Simulation results and the decoding complexity analysis show that although the Rate-Compatible/Quasi-Cyclic (RC/QC)-LDPC code employing an offset layered belief propagation (BP) method can reduce the computational complexity by approximately 30% for the channel coding rate of R ≥ 1/2, the required average received signal energy per bit-to-noise power spectrum density ratio (Eb/N0) is degraded by approximately 0.2-0.3 dB for R = 1/3, 1/2 and 3/4 compared to that for the turbo code. Moreover, the decoding complexity level of the RC/QC-LDPC code with the δ-min algorithm is almost the same or higher than that for the turbo code with a slight degradation in the required received Eb/N0. Although the decoding complexity level of the ZigZag code is lower than that of the turbo code, the code brings about a distinct loss in the required average received Eb/N0 of approximately 0.4 dB. Finally, the turbo Single Parity Check (SPC) code improves the BLER performance compared to the ZigZag code, i.e., achieves almost the same BLER performance as that for the turbo code, at the cost of a two-fold increase in the decoding complexity. As a result, we conclude that the turbo code with a contention free interleaver is more promising than the LDPC codes for prioritizing the achievable performance over complexity and as the channel coding scheme for the shared data channel in the E-UTRA.

A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18 µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200 MHz. The corresponding power consumption of DCPLL is 3.71 mW.