The wireless LAN standards of HiperLAN2 and HiSWANa provide wireless access with high data rates in the 5 GHz band. The specifications of these standards include connection control procedures but do not define them in detail. In this paper, practical procedures and additional functions of connection control are described, such as efficient DUC bandwidth control for unicast and multicast, non-authenticated multicast, and authentication with the AAA server. These procedures and functions exceed the scope of HiperLAN2 and HiSWANa standards. Ways of implementing these connection control procedures efficiently are also provided.

Hot spot service based on wireless LANs is expected to play an important role in the beyond 3G wireless networks. Although spatial coverage is very limited, a comfortable and higher speed compared with a cellular system is available there. However, there might exist nodes that cannot communicate directly with an Access Point (AP) because of the distant location or the shadowing due to obstacles. Accordingly, the introduction of two-hop relaying to the hot spot is useful to extend the coverage and avoid the dead spot. However, the throughput per node is getting decreased as the hot spot coverage area increases. Therefore, in this paper, we propose a scheme to reuse the same channel spatially wherever possible and apply it to the HiperLAN/2 based wireless LAN hot spot with two-hop relaying to compensate for the decrease of the throughput per node. Namely, we modify the HiperLAN/2 protocol in such a way that a time slot is reused at the nodes spatially separated far enough not to cause packet collision. Thus, the throughput is expected to be improved and confirmed by a theoretical analysis and computer simulations.

This paper describes the design, fabrication, and measurement of a multiple U-shaped slot antenna for Hiper-LAN. The prototype consists of a U-shaped slot and two inverted U-shaped slot. To obtain sufficient bandwidth, a foam layer is inserted between the ground plane and substrate. A measured bandwidth of approximately 7.6% (VSWR 1.5) and gain of 2.9-5.3 dBi are obtained. The experimental far-field patterns are shown to be stable across the pass band, with the 3 dB beam width in azimuth and elevation at 50and 62, respectively.

This letter derives low-complexity frame and coarse frequency-offset synchronization techniques for orthogonal frequency division multiplexing (OFDM)-based HIPERLAN (HIgh PErformance Radio LAN) system. We first propose a frame detector structure directly based on the correlation method and a reduced complexity structure having the similar performance compared with conventional correlation method. We then propose a coarse frequency-offset synchronization technique and show the performance of the proposed techniques by simulation.

In this paper, the performance of HIPERLAN (HIgh PErformance Radio Local Area Networks) CAC (Channel Access Control) of ETSI (European Telecommunication Standards Institute) in Europe, as High speed wireless LAN, is analyzed mathematically. The CAC protocol of HIPERLAN is the EY-NPMA (Elimination Yield-Nonpreemptive Priority Multiple Access) in which data is transmitted after prioritization, elimination and yield phase. We analyzed channel contention phase composed of elimination and yield phase and then throughput is inspected by simulation. This result is useful to design and implement of Ad hoc wireless networks.

In this paper, the iterative decoding of BCH product codes also called Block Turbo Codes (BTC) is evaluated for the HIPERLAN/2 OFDM system. Simulations show that expurgated BCH codes should be chosen as constituent codes in order to outperform the specified convolutional code. We also show that the bit-by-bit frequency interleaver has a big impact on the behaviour of the turbo decoding process and that increasing its size together with time diversity lead to good performance when compared to the convolutional code.

This paper presents the HiperSonic 1, a multi-standard, application-specific signal processor, designed to execute the baseband conversion algorithms in IEEE802.11a- and HIPERLAN/2-based 5 GHz wireless LAN applications. In contrast to widely existing, dedicated implementations, most of the computational effort here was mapped onto a configurable, data- and instruction-parallel DSP core. The core is supplemented by mixed signal A/D, D/A converters and hardware accelerators. Memory and register architecture, instruction set and peripheral interfaces of the chip were carefully optimized for the targeted applications, leading to a sound combination of flexibility, die area and power consumption. The 120 MHz, 7.6 million-transistor solution was implemented in 0.18 µm CMOS and performs IEEE802.11a or HiperLAN/2 compliant baseband processing at data rates up to 60 Mbit/s.